| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 57 /// REGISTER_PACKED(OPC)
58 /// \p OPC The VVP opcode of the operation.
60 #define REGISTER_PACKED(OPC)
63 /// ADD_REDUCE_VVP_OP(OPC)
64 /// \p OPC The VVP opcode of the operation.
67 #define ADD_REDUCE_VVP_OP(OPC, SDNAME) ADD_VVP_OP(OPC, SDNAME)
76 #define HELPER_REDUCTION(OPC, SCALAR_OPC) \
77 ADD_REDUCE_VVP_OP(VVP_REDUCE_##OPC,VECREDUCE_##OPC) \
78 HANDLE_VP_TO_VVP(VP_REDUCE_##OPC, VVP_REDUCE_##OPC) \
79 HANDLE_VVP_REDUCE_TO_SCALAR(VVP_REDUCE_##OPC, SCALAR_OPC)
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| H A D | VECustomDAG.cpp | 362 bool hasReductionStartParam(unsigned OPC) { in hasReductionStartParam() argument
364 if (ISD::isVPReduction(OPC)) in hasReductionStartParam()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 22 #define HANDLE_TARGET_OPCODE(OPC) OPC, argument
23 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) IDENT = OPC, argument
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 759 #define HANDLE_TERM_INST(N, OPC, CLASS) OPC = N,
766 #define HANDLE_UNARY_INST(N, OPC, CLASS) OPC = N,
773 #define HANDLE_BINARY_INST(N, OPC, CLASS) OPC = N,
780 #define HANDLE_MEMORY_INST(N, OPC, CLASS) OPC = N,
787 #define HANDLE_CAST_INST(N, OPC, CLASS) OPC = N,
794 #define HANDLE_FUNCLETPAD_INST(N, OPC, CLASS) OPC = N,
801 #define HANDLE_OTHER_INST(N, OPC, CLASS) OPC = N,
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| H A D | InstrTypes.h | 137 #define HANDLE_UNARY_INST(N, OPC, CLASS) \
139 return Create(Instruction::OPC, V, Name);\
142 #define HANDLE_UNARY_INST(N, OPC, CLASS) \
145 return Create(Instruction::OPC, V, Name, BB);\
148 #define HANDLE_UNARY_INST(N, OPC, CLASS) \
151 return Create(Instruction::OPC, V, Name, I);\
229 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
232 return Create(Instruction::OPC, V1, V2, Name);\
235 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
241 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
[all …]
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| H A D | VPIntrinsics.def | 93 // \p OPC The opcode of the instruction with the same function.
95 #define VP_PROPERTY_FUNCTIONAL_OPC(OPC)
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | Instruction.cpp | 779 #define HANDLE_TERM_INST(N, OPC, CLASS) \ in getNumSuccessors() argument
780 case Instruction::OPC: \ in getNumSuccessors()
791 #define HANDLE_TERM_INST(N, OPC, CLASS) \ in getSuccessor() argument
792 case Instruction::OPC: \ in getSuccessor()
803 #define HANDLE_TERM_INST(N, OPC, CLASS) \ in setSuccessor() argument
804 case Instruction::OPC: \ in setSuccessor()
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| H A D | IntrinsicInst.cpp | 460 #define VP_PROPERTY_FUNCTIONAL_OPC(OPC) return Instruction::OPC; in getFunctionalOpcodeForVP() argument
473 #define VP_PROPERTY_FUNCTIONAL_OPC(OPC) case Instruction::OPC: in getForOpcode() argument
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| H A D | Value.cpp | 124 #define HANDLE_INST(N, OPC, CLASS) \ in deleteValue() argument
125 case Value::InstructionVal + Instruction::OPC: \ in deleteValue()
128 #define HANDLE_USER_INST(N, OPC, CLASS) in deleteValue() argument
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 576 const int OPC = TLI->InstructionOpcodeToISD(FAdd->getOpcode()); in getArithmeticInstrCost() local
577 if (OPC == ISD::FADD || OPC == ISD::FSUB) { in getArithmeticInstrCost()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 299 #define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC in OpcodeCache() argument
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 480 #define HANDLE_TARGET_OPCODE(OPC) #OPC, argument
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| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | TargetOpcodes.def | 18 #define HANDLE_TARGET_OPCODE(OPC, NUM)
24 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | README.txt | 586 OP_type is the operand type - one of OPC (opcode), RD (register destination),
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 11162 // SWP SZ |111000|A |R |1 |Rs |1 |OPC|00|Rn |Rt
11163 // LD SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |Rt
11164 // ST SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |11111
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