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Searched refs:NumRegs (Results 1 – 25 of 70) sorted by relevance

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/llvm-project-15.0.7/bolt/include/bolt/Passes/
H A DLivenessAnalysis.h36 NumRegs(BF.getBinaryContext().MRI->getNumRegs()) {} in LivenessAnalysis()
53 BitVector GPRegs(NumRegs, false); in scavengeRegAfter()
68 const uint16_t NumRegs; variable
76 BitVector State(NumRegs, false); in getStartingStateAtBB()
86 return BitVector(NumRegs, false); in getStartingStateAtBB()
90 return BitVector(NumRegs, false); in getStartingStateAtPoint()
101 BitVector Written = BitVector(NumRegs, false); in computeNext()
116 BitVector CSR = BitVector(NumRegs, false); in computeNext()
130 BitVector Used = BitVector(NumRegs, false); in computeNext()
H A DStokeInfo.h110 uint16_t NumRegs; variable
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp111 unsigned NumRegs = RC->getNumRegs(); in compute() local
114 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
143 RCI.NumRegs = N + CSRAlias.size(); in compute()
144 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
157 if (StressRA && RCI.NumRegs > StressRA) in compute()
158 RCI.NumRegs = StressRA; in compute()
163 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
171 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
H A DExecutionDomainFix.cpp71 assert(unsigned(rx) < NumRegs && "Invalid index"); in setLiveReg()
82 assert(unsigned(rx) < NumRegs && "Invalid index"); in kill()
92 assert(unsigned(rx) < NumRegs && "Invalid index"); in force()
122 for (unsigned rx = 0; rx != NumRegs; ++rx) in collapse()
144 for (unsigned rx = 0; rx != NumRegs; ++rx) { in merge()
160 LiveRegs.assign(NumRegs, nullptr); in enterBasicBlock()
178 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
420 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); in runOnMachineFunction()
H A DCFIInstrInserter.cpp154 unsigned NumRegs = TRI.getNumRegs(); in calculateCFAInfo() local
164 MBBInfo.IncomingCSRSaved.resize(NumRegs); in calculateCFAInfo()
165 MBBInfo.OutgoingCSRSaved.resize(NumRegs); in calculateCFAInfo()
184 unsigned NumRegs = TRI.getNumRegs(); in calculateOutgoingCFAInfo() local
185 BitVector CSRSaved(NumRegs), CSRRestored(NumRegs); in calculateOutgoingCFAInfo()
H A DLiveVariables.cpp423 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
558 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) { in runOnBlock() argument
606 for (unsigned i = 0; i != NumRegs; ++i) in runOnBlock()
616 const unsigned NumRegs = TRI->getNumRegs(); in runOnMachineFunction() local
617 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
618 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
638 runOnBlock(MBB, NumRegs); in runOnMachineFunction()
640 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
641 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
H A DRDFRegisters.cpp204 unsigned NumRegs = TRI.getNumRegs(); in aliasMM() local
208 for (unsigned w = 0, nw = NumRegs/32; w != nw; ++w) { in aliasMM()
219 unsigned TailRegs = NumRegs % 32; in aliasMM()
222 unsigned TW = NumRegs / 32; in aliasMM()
H A DVirtRegMap.cpp79 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow() local
80 Virt2PhysMap.resize(NumRegs); in grow()
81 Virt2StackSlotMap.resize(NumRegs); in grow()
82 Virt2SplitMap.resize(NumRegs); in grow()
H A DMachineRegisterInfo.cpp46 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); in MachineRegisterInfo() local
49 UsedPhysRegMask.resize(NumRegs); in MachineRegisterInfo()
50 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]()); in MachineRegisterInfo()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp88 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
111 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
113 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
117 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
121 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
127 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
128 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
144 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
146 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
148 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
[all …]
/llvm-project-15.0.7/bolt/lib/Passes/
H A DStokeInfo.cpp48 BitVector RegV(NumRegs, false); in checkInstr()
160 NumRegs = BC.MRI->getNumRegs(); in runOnFunctions()
161 assert(NumRegs > 0 && "STOKE-INFO: the target register number is incorrect!"); in runOnFunctions()
163 DefaultDefInMask.resize(NumRegs, false); in runOnFunctions()
164 DefaultLiveOutMask.resize(NumRegs, false); in runOnFunctions()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp108 unsigned NumRegs = 1; in getRegistersForValue() local
110 NumRegs = in getRegistersForValue()
129 for (; NumRegs; --NumRegs, ++I) { in getRegistersForValue()
552 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm() local
554 assert(NumRegs == SourceRegs.size() && in lowerInlineAsm()
558 if (NumRegs > 1) { in lowerInlineAsm()
564 unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, NumRegs); in lowerInlineAsm()
579 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm() local
580 if (NumRegs > 0) { in lowerInlineAsm()
582 InlineAsm::getFlagWord(InlineAsm::Kind_Clobber, NumRegs); in lowerInlineAsm()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h32 unsigned NumRegs = 0; member
41 return makeArrayRef(Order.get(), NumRegs);
96 return get(RC).NumRegs; in getNumAllocatableRegs()
H A DExecutionDomainFix.h125 const unsigned NumRegs; variable
140 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {} in ExecutionDomainFix()
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp65 unsigned NumRegs) in RegisterFile() argument
69 initialize(SM, NumRegs);
72 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize() argument
77 RegisterFiles.emplace_back(NumRegs); in initialize()
674 unsigned NumRegs = NumPhysRegs[I]; in isAvailable() local
675 if (!NumRegs) in isAvailable()
685 if (RMT.NumPhysRegs < NumRegs) { in isAvailable()
698 NumRegs = RMT.NumPhysRegs; in isAvailable()
701 if (RMT.NumPhysRegs < (RMT.NumUsedPhysRegs + NumRegs)) in isAvailable()
/llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/
H A DReduceRegisterMasks.cpp25 const unsigned NumRegs = TRI->getNumRegs(); in reduceMasksInFunction() local
44 for (unsigned I = 0; I != NumRegs; ++I) { in reduceMasksInFunction()
/llvm-project-15.0.7/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.h387 unsigned NumRegs; variable
470 SlotNo += NumRegs; in getLocID()
480 SlotNo += NumRegs; in getSpillIDWithIdx()
486 assert(ID >= NumRegs); in locIDToSpill()
487 ID -= NumRegs; in locIDToSpill()
495 assert(ID >= NumRegs); in locIDToSpillIdx()
496 ID -= NumRegs; in locIDToSpillIdx()
543 LocIDToLocIdx.resize(NumRegs, LocIdx::MakeIllegalLoc()); in clear()
634 bool isSpill(LocIdx Idx) const { return LocIdxToLocID[Idx] >= NumRegs; } in isSpill()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp231 unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps; in EmitTargetCodeForMemcpy() local
234 DAG.getConstant(NumRegs, dl, MVT::i32)); in EmitTargetCodeForMemcpy()
238 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
239 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h157 unsigned NumRegs; // Number of entries in the array variable
367 NumRegs = NR; in InitMCRegisterInfo()
447 assert(RegNo < NumRegs &&
492 return NumRegs; in getNumRegs()
554 assert(RegNo < NumRegs && in getEncodingValue()
/llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h229 void initialize(const MCSchedModel &SM, unsigned NumRegs);
233 unsigned NumRegs = 0);
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp50 unsigned NumRegs = TLI.getNumRegisters(Ctx, VT); in computeLegalValueVTs() local
52 for (unsigned I = 0; I != NumRegs; ++I) in computeLegalValueVTs()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp199 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag); in tryInlineAsm() local
200 if (NumRegs) in tryInlineAsm()
217 || NumRegs != 2) in tryInlineAsm()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp154 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag); in selectInlineAsm() local
155 if (NumRegs) in selectInlineAsm()
183 NumRegs != 2) in selectInlineAsm()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallingConv.cpp243 static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]); in CC_X86_32_MCUInReg() local
278 bool UseRegs = PendingMembers.size() <= std::min(2U, NumRegs - FirstFree); in CC_X86_32_MCUInReg()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1349 unsigned NumRegs = 0; in printMatrixTileList() local
1352 ++NumRegs; in printMatrixTileList()
1361 if (Printed + 1 != NumRegs) in printMatrixTileList()
1378 unsigned NumRegs = 1; in printVectorList() local
1382 NumRegs = 2; in printVectorList()
1386 NumRegs = 3; in printVectorList()
1390 NumRegs = 4; in printVectorList()
1408 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) { in printVectorList()
1414 if (i + 1 != NumRegs) in printVectorList()

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