| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 158 Instruction *Ret = NewShift; in reassociateShiftAmtsOfTwoSameDirectionShifts()
160 Builder.Insert(NewShift); in reassociateShiftAmtsOfTwoSameDirectionShifts()
319 return NewShift; in dropRedundantMaskingOfLeftShiftInput()
321 Builder.Insert(NewShift); in dropRedundantMaskingOfLeftShiftInput()
399 if (auto *NewShift = cast_or_null<Instruction>( in commonShiftTransforms() local
401 return NewShift; in commonShiftTransforms()
774 Value *NewShift = in FoldShiftByConstant() local
776 NewShift->takeName(Op0BO); in FoldShiftByConstant()
805 return SelectInst::Create(Cond, NewOp, NewShift); in FoldShiftByConstant()
1006 Value *NewShift = Builder.CreateShl(X, Op1); in visitShl() local
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| H A D | InstCombineCompares.cpp | 1737 Value *NewShift = in foldICmpAndShift() local
1742 Value *NewAnd = Builder.CreateAnd(Shift->getOperand(0), NewShift); in foldICmpAndShift()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3095 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine() local
3099 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
3119 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine() local
3122 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
3129 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine() local
3131 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
3179 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine() local
3181 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1996 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in foldMaskedShiftToScaledMask() local
2005 insertDAGNode(DAG, N, NewShift); in foldMaskedShiftToScaledMask()
2006 DAG.ReplaceAllUsesWith(N, NewShift); in foldMaskedShiftToScaledMask()
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| H A D | X86ISelLowering.cpp | 41695 SDValue NewShift = TLO.DAG.getNode( in SimplifyDemandedBitsForTargetNode() local
41698 return TLO.CombineTo(Op, NewShift); in SimplifyDemandedBitsForTargetNode()
46724 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1); in combineShiftRightLogical() local
46725 return DAG.getNode(ISD::AND, DL, VT, NewShift, NewMask); in combineShiftRightLogical()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 2397 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit() local
2399 return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC); in foldAddSubOfSignBit()
6138 SDValue NewShift = DAG.getNode(ShiftOpcode, DL, VT, LogicX, Y); in foldLogicOfShifts() local
6139 return DAG.getNode(LogicOpcode, DL, VT, NewShift, Z); in foldLogicOfShifts()
8755 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant() local
8757 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
9514 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
9516 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift); in visitSRL()
9524 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
9529 SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); in visitSRL()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 17171 SDValue NewShift = DAG.getNode(NewOpcode, DL, N->getVTList(), Op0, Op1, in PerformLongShiftCombine() local
17173 DAG.ReplaceAllUsesWith(N, NewShift.getNode()); in PerformLongShiftCombine()
17174 return NewShift; in PerformLongShiftCombine()
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