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Searched refs:NewOpc (Results 1 – 25 of 71) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp524 unsigned NewOpc; in Lower() local
532 OutMI.setOpcode(NewOpc); in Lower()
556 unsigned NewOpc; in Lower() local
573 OutMI.setOpcode(NewOpc); in Lower()
581 unsigned NewOpc; in Lower() local
587 OutMI.setOpcode(NewOpc); in Lower()
624 unsigned NewOpc; in Lower() local
689 OutMI.setOpcode(NewOpc); in Lower()
696 unsigned NewOpc; in Lower() local
860 unsigned NewOpc; in Lower() local
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H A DX86EvexToVex.cpp150 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc, in performCustomAdjustments() argument
152 (void)NewOpc; in performCustomAdjustments()
159 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
175 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr || in performCustomAdjustments()
176 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) && in performCustomAdjustments()
261 unsigned NewOpc = I->VexOpcode; in CompressEvexToVexImpl() local
269 if (!performCustomAdjustments(MI, NewOpc, ST)) in CompressEvexToVexImpl()
272 MI.setDesc(TII->get(NewOpc)); in CompressEvexToVexImpl()
H A DX86FixupLEAs.cpp795 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
801 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
807 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
833 unsigned NewOpc = in processInstrForSlow3OpLEA() local
835 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
839 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local
840 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
867 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
868 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
890 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
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H A DX86InstructionSelector.cpp533 if (NewOpc == Opc) in selectLoadStoreOp()
539 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
575 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
627 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
657 unsigned NewOpc; in selectConstant() local
660 NewOpc = X86::MOV8ri; in selectConstant()
663 NewOpc = X86::MOV16ri; in selectConstant()
666 NewOpc = X86::MOV32ri; in selectConstant()
671 NewOpc = X86::MOV64ri32; in selectConstant()
673 NewOpc = X86::MOV64ri; in selectConstant()
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H A DX86ISelDAGToDAG.cpp1058 unsigned NewOpc; in PreprocessISelDAG() local
1091 unsigned NewOpc; in PreprocessISelDAG() local
1113 unsigned NewOpc; in PreprocessISelDAG() local
1117 NewOpc = ISD::SIGN_EXTEND; in PreprocessISelDAG()
1119 NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG()
1506 unsigned NewOpc; in PostprocessISelDAG() local
1549 unsigned NewOpc; in PostprocessISelDAG() local
3319 unsigned NewOpc = in foldLoadStoreIntoMemOperand() local
3409 unsigned NewOpc = SelectRegOpcode(Opc); in foldLoadStoreIntoMemOperand() local
3433 NewOpc = SelectImm8Opcode(Opc); in foldLoadStoreIntoMemOperand()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp224 unsigned OpNum, NewOpc; in rewrite() local
227 NewOpc = Hexagon::L2_loadri_io; in rewrite()
231 NewOpc = Hexagon::L2_loadrd_io; in rewrite()
235 NewOpc = Hexagon::V6_vL32b_ai; in rewrite()
239 NewOpc = Hexagon::S2_storeri_io; in rewrite()
243 NewOpc = Hexagon::S2_storerd_io; in rewrite()
247 NewOpc = Hexagon::V6_vS32b_ai; in rewrite()
273 MI.setDesc(HII.get(NewOpc)); in rewrite()
H A DHexagonGenPredicate.cpp387 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
389 if (NewOpc == 0) { in convertToPredForm()
392 NewOpc = Hexagon::C2_not; in convertToPredForm()
395 NewOpc = TargetOpcode::COPY; in convertToPredForm()
422 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); in convertToPredForm()
H A DHexagonCopyToCombine.cpp863 unsigned NewOpc; in emitCombineRR() local
865 NewOpc = Hexagon::A2_combinew; in emitCombineRR()
868 NewOpc = Hexagon::V6_vcombine; in emitCombineRR()
872 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg) in emitCombineRR()
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp3678 unsigned NewOpc; in processInstruction() local
3695 Inst.setOpcode(NewOpc); in processInstruction()
3707 unsigned NewOpc; in processInstruction() local
3713 Inst.setOpcode(NewOpc); in processInstruction()
3728 unsigned NewOpc; in processInstruction() local
3731 case X86::RCR8ri: NewOpc = X86::RCR8r1; break; in processInstruction()
3732 case X86::RCR16ri: NewOpc = X86::RCR16r1; break; in processInstruction()
3733 case X86::RCR32ri: NewOpc = X86::RCR32r1; break; in processInstruction()
3762 TmpInst.setOpcode(NewOpc); in processInstruction()
3781 unsigned NewOpc; in processInstruction() local
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp684 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
706 switch (NewOpc) { in genInstrWithNewOpc()
708 NewOpc = Mips::BEQZC; in genInstrWithNewOpc()
711 NewOpc = Mips::BNEZC; in genInstrWithNewOpc()
714 NewOpc = Mips::BGEZC; in genInstrWithNewOpc()
717 NewOpc = Mips::BLTZC; in genInstrWithNewOpc()
720 NewOpc = Mips::BEQZC64; in genInstrWithNewOpc()
723 NewOpc = Mips::BNEZC64; in genInstrWithNewOpc()
734 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc()
735 NewOpc == Mips::JIALC64) { in genInstrWithNewOpc()
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H A DMipsSEInstrInfo.h98 unsigned NewOpc) const;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1500 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1543 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1637 unsigned NewOpc; in MergeBaseUpdateLSDouble() local
1653 if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) { in MergeBaseUpdateLSDouble()
1656 assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST); in MergeBaseUpdateLSDouble()
1806 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1830 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
2268 NewOpc = ARM::LDRD; in CanFormLdStDWord()
2270 NewOpc = ARM::STRD; in CanFormLdStDWord()
2272 NewOpc = ARM::t2LDRDi8; in CanFormLdStDWord()
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H A DARMConstantIslandPass.cpp1831 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1852 if (!NewOpc) in optimizeThumb2Instructions()
1882 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1888 NewOpc = ARM::tB; in optimizeThumb2Branches()
1893 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1898 if (NewOpc) { in optimizeThumb2Branches()
1916 unsigned NewOpc = 0; in optimizeThumb2Branches() member
1922 ImmCmp.NewOpc = 0; in optimizeThumb2Branches()
1930 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1954 ImmCmp.NewOpc = NewOpc; in optimizeThumb2Branches()
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H A DThumb2InstrInfo.cpp588 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex() local
590 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
621 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
631 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
644 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
649 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
709 if (NewOpc != Opcode) in rewriteT2FrameIndex()
710 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
754 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
H A DARMInstructionSelector.cpp899 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); in select() local
900 if (NewOpc == I.getOpcode()) in select()
902 I.setDesc(TII.get(NewOpc)); in select()
1095 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select() local
1096 if (NewOpc == G_LOAD || NewOpc == G_STORE) in select()
1099 I.setDesc(TII.get(NewOpc)); in select()
1101 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH) in select()
H A DARMExpandPseudoInsts.cpp894 unsigned NewOpc = in ExpandMQQPRLoadStore() local
899 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMQQPRLoadStore()
920 if (NewOpc == ARM::VSTMDIA) in ExpandMQQPRLoadStore()
2348 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
2389 unsigned NewOpc; in ExpandMI() local
2391 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
2392 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
2393 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
2394 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
2670 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
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H A DThumbRegisterInfo.cpp416 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
417 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex()
418 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp143 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); in optimizeNZCVDefs() local
147 if (InsideCmpRange && NewOpc) { in optimizeNZCVDefs()
151 II.setDesc(TII->get(NewOpc)); in optimizeNZCVDefs()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
293 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); in transformInstruction()
362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst) in transformInstruction()
H A DAArch64CondBrTuning.cpp97 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit); in convertToFlagSetting() local
103 TII->get(NewOpc), NewDestReg); in convertToFlagSetting()
H A DAArch64FrameLowering.cpp1126 unsigned NewOpc; in convertCalleeSaveRestoreToSPPrePostIncDec() local
1131 NewOpc = AArch64::STPXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
1134 NewOpc = AArch64::STPDpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
1137 NewOpc = AArch64::STPQpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
1140 NewOpc = AArch64::STRXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
1143 NewOpc = AArch64::STRDpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
1146 NewOpc = AArch64::STRQpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
1149 NewOpc = AArch64::LDPXpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
1152 NewOpc = AArch64::LDPDpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
1155 NewOpc = AArch64::LDPQpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local
255 assert(NewOpc != 0 && "Unknown merged node opcode"); in insertMergedInstruction()
259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc)); in insertMergedInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp283 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN() local
293 assert(MI.getOpcode() != NewOpc); in applyCvtF32UByteN()
294 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
H A DSIInstrInfo.cpp1046 int NewOpc; in commuteOpcode() local
1050 if (NewOpc != -1) in commuteOpcode()
1052 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode()
1056 if (NewOpc != -1) in commuteOpcode()
1058 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode()
2998 unsigned NewOpc = in FoldImmediate() local
3077 unsigned NewOpc = in FoldImmediate() local
3361 unsigned NewOpc = in convertToThreeAddress() local
3377 unsigned NewOpc = IsFMA in convertToThreeAddress() local
5338 if (NewOpc < 0) in moveFlatAddrToVGPR()
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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp653 unsigned NewOpc = Node->getOpcode(); in PromoteFP_TO_INT() local
656 if (NewOpc == ISD::FP_TO_UINT && in PromoteFP_TO_INT()
658 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
660 if (NewOpc == ISD::STRICT_FP_TO_UINT && in PromoteFP_TO_INT()
662 NewOpc = ISD::STRICT_FP_TO_SINT; in PromoteFP_TO_INT()
667 Promoted = DAG.getNode(NewOpc, dl, {NVT, MVT::Other}, in PromoteFP_TO_INT()
671 Promoted = DAG.getNode(NewOpc, dl, NVT, Node->getOperand(0)); in PromoteFP_TO_INT()
678 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT()
680 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT()
682 Promoted = DAG.getNode(NewOpc, dl, NVT, Promoted, in PromoteFP_TO_INT()

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