Lines Matching refs:NewOpc
1348 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1500 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1502 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1504 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1510 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1512 (!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) { in MergeBaseUpdateLoadStore()
1513 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1514 if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII)) in MergeBaseUpdateLoadStore()
1530 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
1543 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1545 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
1557 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
1570 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
1584 if (isAM2 && NewOpc == ARM::STR_POST_IMM) { in MergeBaseUpdateLoadStore()
1587 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base) in MergeBaseUpdateLoadStore()
1598 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base) in MergeBaseUpdateLoadStore()
1637 unsigned NewOpc; in MergeBaseUpdateLSDouble() local
1639 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1644 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1645 if (!isLegalAddressImm(NewOpc, Offset, TII)) in MergeBaseUpdateLSDouble()
1652 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)); in MergeBaseUpdateLSDouble()
1653 if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) { in MergeBaseUpdateLSDouble()
1656 assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST); in MergeBaseUpdateLSDouble()
1662 TII->get(NewOpc).getNumOperands() == 7 && in MergeBaseUpdateLSDouble()
1734 bool isDef, unsigned NewOpc, unsigned Reg, in InsertLDR_STR() argument
1741 TII->get(NewOpc)) in InsertLDR_STR()
1750 TII->get(NewOpc)) in InsertLDR_STR()
1806 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1810 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc)) in FixInvalidRegPairOp()
1818 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc)) in FixInvalidRegPairOp()
1830 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1844 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill, in FixInvalidRegPairOp()
1858 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill, in FixInvalidRegPairOp()
2058 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM() local
2061 PrevMI.setDesc(TII->get(NewOpc)); in MergeReturnIntoLDM()
2172 unsigned &NewOpc, Register &EvenReg, Register &OddReg,
2257 MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, in CanFormLdStDWord() argument
2268 NewOpc = ARM::LDRD; in CanFormLdStDWord()
2270 NewOpc = ARM::STRD; in CanFormLdStDWord()
2272 NewOpc = ARM::t2LDRDi8; in CanFormLdStDWord()
2276 NewOpc = ARM::t2STRDi8; in CanFormLdStDWord()
2424 unsigned NewOpc = 0; in RescheduleOps() local
2427 if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc, in RescheduleOps()
2433 const MCInstrDesc &MCID = TII->get(NewOpc); in RescheduleOps()