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Searched refs:N01 (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/clang/test/Modules/Inputs/stress1/
H A Dcommon.h8 namespace N01 { struct S00; }
44 namespace N01 {
/llvm-project-15.0.7/clang/test/Modules/
H A Dstress1.cpp131 int f() { return N01::S00('a').method00('b') + (int)N00::S00(42) + function00(42) + g(); } in f()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1092 SDValue N01 = N0.getOperand(1); in reassociateOpsCommutative() local
1115 if (N1 == N00 || N1 == N01) in reassociateOpsCommutative()
1121 return N01; in reassociateOpsCommutative()
1123 if (N1 == N01) in reassociateOpsCommutative()
1128 if (N1 != N01) { in reassociateOpsCommutative()
5068 SDValue N00, N01, N02, N03; in isSaturatingMinMax() local
5074 N01 = N03 = N0.getOperand(1); in isSaturatingMinMax()
5079 N01 = N0.getOperand(1); in isSaturatingMinMax()
8509 N01 = DAG.getNode(ISD::XOR, SDLoc(N01), VT, N01, N1); // N01 = ~N01 in visitXOR()
8521 N01 = DAG.getNode(ISD::XOR, SDLoc(N01), VT, N01, N1); // N01 = ~N01 in visitXOR()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2381 SDValue N01 = N0.getOperand(1); in doPeepholeSExtW() local
2385 !isUInt<5>(cast<ConstantSDNode>(N01)->getSExtValue())) in doPeepholeSExtW()
2390 N00, N01); in doPeepholeSExtW()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp46648 SDValue N01 = N0.getOperand(1); in combineShiftRightArithmetic() local
47525 SDValue N01 = N0.getOperand(1); in convertIntLogicToFPLogic() local
48374 SDValue N01 = N0->getOperand(1); in foldMaskedMerge() local
50429 SDValue N01 = N0.getOperand(1); in detectPMADDUBSW() local
50436 std::swap(N00, N01); in detectPMADDUBSW()
50449 N01 = N01.getOperand(0); in detectPMADDUBSW()
50478 SDValue N01Elt = N01.getOperand(i); in detectPMADDUBSW()
51873 SDValue N01 = N0.getOperand(1); in combineZext() local
51877 (N01.isUndef() || DAG.MaskedValueIsZero(N01, ZeroMask))) { in combineZext()
53403 SDValue N01 = N0.getOperand(1); in matchPMADDWD_2() local
[all …]
H A DX86ISelDAGToDAG.cpp3633 SDValue N01 = N0->getOperand(1); in matchBitExtract() local
3635 if (N1 != N01) in matchBitExtract()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4406 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
4412 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
15140 SDValue N01 = N0->getOperand(IsStrict ? 2 : 1); in performExtractVectorEltCombine() local
15142 ShuffleVectorSDNode *Shuffle = dyn_cast<ShuffleVectorSDNode>(N01); in performExtractVectorEltCombine()
15148 Other = N01; in performExtractVectorEltCombine()
15275 SDValue N01 = N0->getOperand(1); in performConcatVectorsCombine() local
15283 N01->getOpcode() == ISD::EXTRACT_SUBVECTOR && in performConcatVectorsCombine()
15287 SDValue N01Source = N01->getOperand(0); in performConcatVectorsCombine()
15296 uint64_t N01Index = N01.getConstantOperandVal(1); in performConcatVectorsCombine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9533 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
9539 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
13909 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
13912 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()