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Searched refs:MemIndexedMode (Results 1 – 25 of 30) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1251 SDValue Offset, ISD::MemIndexedMode AM);
1271 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1341 SDValue Offset, ISD::MemIndexedMode AM);
1350 getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1384 SDValue Offset, ISD::MemIndexedMode AM);
1387 MachineMemOperand *MMO, ISD::MemIndexedMode AM,
1398 SDValue Offset, ISD::MemIndexedMode AM);
1449 ISD::MemIndexedMode AM);
1469 ISD::MemIndexedMode AM);
1480 MachineMemOperand *MMO, ISD::MemIndexedMode AM,
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H A DSelectionDAGNodes.h1000 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
2294 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2307 ISD::MemIndexedMode getAddressingMode() const {
2328 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2356 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2390 ISD::MemIndexedMode AM, EVT MemVT,
2444 ISD::MemIndexedMode getAddressingMode() const {
2495 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2598 ISD::MemIndexedMode AM, EVT MemVT,
2617 ISD::MemIndexedMode getAddressingMode() const {
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H A DISDOpcodes.h1373 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enum
H A DBasicTTIImpl.h177 static ISD::MemIndexedMode getISDIndexedMode(TTI::MemIndexedMode M) { in getISDIndexedMode()
339 bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty, in isIndexedLoadLegal()
345 bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty, in isIndexedStoreLegal()
H A DTargetLowering.h3453 ISD::MemIndexedMode &/*AM*/, in getPreIndexedAddressParts() argument
3464 ISD::MemIndexedMode &/*AM*/, in getPostIndexedAddressParts() argument
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.h107 ISD::MemIndexedMode &AM,
111 SDValue &Offset, ISD::MemIndexedMode &AM,
H A DAVRISelDAGToDAG.cpp123 ISD::MemIndexedMode AM = LD->getAddressingMode(); in selectIndexedLoad()
H A DAVRISelLowering.cpp932 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
989 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h185 ISD::MemIndexedMode &AM,
H A DMSP430ISelDAGToDAG.cpp298 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
H A DMSP430ISelLowering.cpp1341 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h1356 enum MemIndexedMode { enum
1365 bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const;
1368 bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const;
1811 virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const = 0;
1812 virtual bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const = 0;
2403 bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const override { in isIndexedLoadLegal()
2406 bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const override { in isIndexedStoreLegal()
H A DTargetTransformInfoImpl.h747 bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, in isIndexedLoadLegal()
752 bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, in isIndexedStoreLegal()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h1114 ISD::MemIndexedMode &AM, bool &IsInc,
1117 ISD::MemIndexedMode &AM,
1120 SDValue &Offset, ISD::MemIndexedMode &AM,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h503 ISD::MemIndexedMode &AM,
510 SDValue &Offset, ISD::MemIndexedMode &AM,
H A DARMISelDAGToDAG.cpp824 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg()
860 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre()
880 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm()
959 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset()
1079 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1388 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset()
1440 ISD::MemIndexedMode AM; in SelectT2AddrModeImm7Offset()
1584 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryARMIndexedLoad()
1664 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT1IndexedLoad()
1690 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT2IndexedLoad()
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H A DARMInstrMVE.td7120 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7125 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7204 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7219 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp1031 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode, in isIndexedLoadLegal()
1036 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode, in isIndexedStoreLegal()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7862 ISD::MemIndexedMode AM) { in getIndexedLoad()
7995 ISD::MemIndexedMode AM) { in getIndexedStore()
8045 SDValue SelectionDAG::getLoadVP(ISD::MemIndexedMode AM, in getLoadVP()
8125 ISD::MemIndexedMode AM) { in getIndexedLoadVP()
8247 ISD::MemIndexedMode AM) { in getIndexedStoreVP()
8376 ISD::MemIndexedMode AM) { in getIndexedStridedLoadVP()
8396 ISD::MemIndexedMode AM, in getStridedStoreVP()
8499 ISD::MemIndexedMode AM) { in getIndexedStridedStoreVP()
8619 ISD::MemIndexedMode AM, in getMaskedLoad()
8652 ISD::MemIndexedMode AM) { in getIndexedMaskedLoad()
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H A DSelectionDAGDumper.cpp502 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h269 ISD::MemIndexedMode &AM,
H A DHexagonISelDAGToDAG.cpp450 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad()
559 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
H A DHexagonISelLowering.cpp629 SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1206 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1217 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1258 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1264 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h837 ISD::MemIndexedMode &AM,

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