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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td41 // Masked.
80 // Masked.
105 // Masked.
122 // Masked.
154 // Masked.
175 // Masked.
284 // Masked.
445 // Masked.
542 // Masked.
579 // Masked.
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h138 uint16_t Masked : 1; member
149 uint16_t Masked : 1; member
160 uint16_t Masked : 1; member
169 uint16_t Masked : 1; member
178 uint16_t Masked : 1; member
188 uint16_t Masked :1; member
196 uint16_t Masked : 1; member
H A DRISCVInstrInfoVPseudos.td466 bits<1> Masked = M;
484 bits<1> Masked = M;
495 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
500 bits<1> Masked = M;
532 bits<1> Masked = M;
551 bits<1> Masked = M;
570 bits<1> Masked = M;
587 bits<1> Masked = M;
840 RISCVVSE</*Masked*/0, /*Strided*/0, log2<EEW>.val, VLMul> {
853 RISCVVSE</*Masked*/1, /*Strided*/0, log2<EEW>.val, VLMul> {
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DCaymanInstructions.td114 let DST_SEL_Y = 7; // Masked
115 let DST_SEL_Z = 7; // Masked
116 let DST_SEL_W = 7; // Masked
124 let DST_SEL_Y = 7; // Masked
125 let DST_SEL_Z = 7; // Masked
126 let DST_SEL_W = 7; // Masked
136 let DST_SEL_Y = 7; // Masked
137 let DST_SEL_Z = 7; // Masked
138 let DST_SEL_W = 7; // Masked
H A DEvergreenInstructions.td189 let DST_SEL_Y = 7; // Masked
190 let DST_SEL_Z = 7; // Masked
191 let DST_SEL_W = 7; // Masked
200 let DST_SEL_Y = 7; // Masked
201 let DST_SEL_Z = 7; // Masked
202 let DST_SEL_W = 7; // Masked
213 let DST_SEL_Y = 7; // Masked
214 let DST_SEL_Z = 7; // Masked
215 let DST_SEL_W = 7; // Masked
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp190 Value *Masked, *ShiftShAmt; in dropRedundantMaskingOfLeftShiftInput() local
192 m_Shift(m_Value(Masked), m_ZExtOrSelf(m_Value(ShiftShAmt)))); in dropRedundantMaskingOfLeftShiftInput()
197 if (match(Masked, m_CombineAnd(m_Trunc(m_Value(Masked)), m_Value(Trunc))) && in dropRedundantMaskingOfLeftShiftInput()
202 Type *WidestTy = Masked->getType(); in dropRedundantMaskingOfLeftShiftInput()
224 if (match(Masked, m_c_And(m_CombineOr(MaskA, MaskB), m_Value(X)))) { in dropRedundantMaskingOfLeftShiftInput()
229 if (!canTryToConstantAddTwoShiftAmounts(OuterShift, ShiftShAmt, Masked, in dropRedundantMaskingOfLeftShiftInput()
254 } else if (match(Masked, m_c_And(m_CombineOr(MaskC, MaskD), m_Value(X))) || in dropRedundantMaskingOfLeftShiftInput()
255 match(Masked, m_Shr(m_Shl(m_Value(X), m_Value(MaskShAmt)), in dropRedundantMaskingOfLeftShiftInput()
261 if (!canTryToConstantAddTwoShiftAmounts(OuterShift, ShiftShAmt, Masked, in dropRedundantMaskingOfLeftShiftInput()
302 if (!Masked->hasOneUse()) in dropRedundantMaskingOfLeftShiftInput()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTypePromotion.cpp622 Value *Masked = Builder.CreateAnd(Trunc->getOperand(0), Mask); in ConvertTruncs() local
624 Masked = Builder.CreateTrunc(Masked, ExtTy); in ConvertTruncs()
626 if (auto *I = dyn_cast<Instruction>(Masked)) in ConvertTruncs()
629 ReplaceAllUsersOfWith(Trunc, Masked); in ConvertTruncs()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-masked-int-arith.ll5 ; Masked Additions
49 ; Masked Subtractions
93 ; Masked multiply-add
141 ; Masked multiply-subtract
H A Dsve-masked-ldst-zext.ll4 ; Masked Loads
95 ; Masked load requires promotion
H A Dsve-masked-ldst-sext.ll5 ; Masked Loads
98 ; Masked load requires promotion
H A DO0-pipeline.ll25 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
H A Dsve-masked-ldst-trunc.ll4 ; Masked Stores
H A Dsve-masked-ldst-nonext.ll4 ; Masked Loads
120 ; Masked load requires promotion
130 ; Masked Stores
238 ; Masked load store of pointer data type
/llvm-project-15.0.7/mlir/include/mlir/Dialect/LLVMIR/
H A DLLVMIntrinsicOps.td354 /// Create a call to Masked Load intrinsic.
369 /// Create a call to Masked Store intrinsic.
382 /// Create a call to Masked Gather intrinsic.
398 /// Create a call to Masked Scatter intrinsic.
411 /// Create a call to Masked Expand Load intrinsic.
416 /// Create a call to Masked Compress Store intrinsic.
/llvm-project-15.0.7/llvm/lib/Support/
H A DAPFixedPoint.cpp38 APInt Masked(NewVal & Mask); in convert() local
41 if (!(Masked == Mask || Masked == 0)) { in convert()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A DO0-pipeline.ll29 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
H A DO3-pipeline.ll57 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
/llvm-project-15.0.7/mlir/test/Integration/Dialect/Vector/CPU/
H A Dtest-maskedload.mlir50 // Masked load tests.
H A Dtest-maskedstore.mlir68 // Masked store tests.
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Hexagon/
H A Dxtype_bit.txt78 # Masked parity
/llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/
H A DMemProfiler.cpp437 if (auto *Masked = dyn_cast<ConstantInt>(Vector->getOperand(Idx))) { in instrumentMaskedLoadOrStore() local
438 if (Masked->isZero()) in instrumentMaskedLoadOrStore()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A DO0-pipeline.ll29 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
/llvm-project-15.0.7/mlir/include/mlir/Dialect/X86Vector/
H A DX86Vector.td67 let summary = "Masked compress op";
120 let summary = "Masked roundscale op";
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp1004 Value *Masked = IC.Builder.CreateAnd(Input, II.getArgOperand(1)); in instCombineIntrinsic() local
1006 Value *Shifted = IC.Builder.CreateLShr(Masked, ShiftAmt); in instCombineIntrinsic()
1050 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1)); in instCombineIntrinsic() local
1051 return IC.replaceInstUsesWith(II, Masked); in instCombineIntrinsic()
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsHexagon.td384 // Masked vector stores

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