| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 66 case ISD::MSTORE: in getVVPOpcode()
203 case ISD::MSTORE: in getMaskPos()
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| H A D | VEISelLowering.cpp | 335 for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE}) in initVPUActions()
1930 case ISD::MSTORE: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 111 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
150 setOperationAction(ISD::MSTORE, P, Custom); in initializeHVXLowering()
192 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
259 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
338 setOperationAction(ISD::MSTORE, BoolW, Custom); in initializeHVXLowering()
1967 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
2151 uint64_t MemSize = (MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE) in SplitHvxMemOp()
2175 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
2198 if (MemOpc == ISD::MSTORE) { in SplitHvxMemOp()
2401 case ISD::MSTORE: in LowerHvxOperation()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1208 MSTORE, enumerator
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| H A D | SelectionDAGNodes.h | 1371 case ISD::MSTORE:
1412 case ISD::MSTORE:
2629 N->getOpcode() == ISD::MSTORE;
2670 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2692 return N->getOpcode() == ISD::MSTORE;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 396 case ISD::MSTORE: return "masked_store"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 2710 case ISD::MSTORE: in SplitVectorOperand()
5435 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break; in WidenVectorOperand()
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| H A D | SelectionDAG.cpp | 779 case ISD::MSTORE: { in AddNodeIDCustom()
8676 AddNodeIDNode(ID, ISD::MSTORE, VTs, Ops); in getMaskedStore()
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| H A D | LegalizeDAG.cpp | 1166 case ISD::MSTORE: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 1656 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N), in PromoteIntegerOperand()
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| H A D | DAGCombiner.cpp | 1793 case ISD::MSTORE: return visitMSTORE(N); in visit()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 595 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
690 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
818 {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); in RISCVTargetLowering()
889 setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE, in RISCVTargetLowering()
3507 case ISD::MSTORE: in LowerOperation()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 664 def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 893 setTargetDAGCombine(ISD::MSTORE); in AArch64TargetLowering()
1247 setOperationAction(ISD::MSTORE, VT, Custom); in AArch64TargetLowering()
1671 setOperationAction(ISD::MSTORE, VT, Custom); in addTypeForFixedLengthSVE()
5532 case ISD::MSTORE: in LowerOperation()
17546 assert((N->getOpcode() == ISD::STORE || N->getOpcode() == ISD::MSTORE) && in foldTruncStoreOfExt()
19564 case ISD::MSTORE: in PerformDAGCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1451 case ISD::MSTORE: in SelectT2AddrModeImm7Offset()
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| H A D | ARMISelLowering.cpp | 265 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
339 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1518 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1724 setOperationAction(ISD::MSTORE, VT, Custom); in X86TargetLowering()
1891 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1898 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
2018 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2352 ISD::MSTORE, in X86TargetLowering()
32350 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG); in LowerOperation()
55065 case ISD::MSTORE: return combineMaskedStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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