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Searched refs:MOReg (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIOptimizeVGPRLiveRange.cpp238 Register MOReg = MO.getReg(); in collectCandidateRegisters() local
240 if (MOReg.isPhysical() || !TRI->isVectorRegister(*MRI, MOReg)) in collectCandidateRegisters()
244 LiveVariables::VarInfo &VI = LV->getVarInfo(MOReg); in collectCandidateRegisters()
253 LiveVariables::VarInfo &VI = LV->getVarInfo(MOReg); in collectCandidateRegisters()
254 if (!VI.isLiveIn(*Endif, MOReg, *MRI)) { in collectCandidateRegisters()
255 KillsInElse.insert(MOReg); in collectCandidateRegisters()
364 Register MOReg = MO.getReg(); in collectWaterfallCandidateRegisters() local
366 if (MOReg.isPhysical() || !TRI->isVectorRegister(*MRI, MOReg)) in collectWaterfallCandidateRegisters()
376 LiveVariables::VarInfo &OldVarInfo = LV->getVarInfo(MOReg); in collectWaterfallCandidateRegisters()
380 OldVarInfo.isLiveIn(*Succ, MOReg, *MRI)) { in collectWaterfallCandidateRegisters()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp860 if (!MOReg) in rescheduleMIBelowKill()
863 Defs.push_back(MOReg); in rescheduleMIBelowKill()
865 Uses.push_back(MOReg); in rescheduleMIBelowKill()
868 Kills.push_back(MOReg); in rescheduleMIBelowKill()
904 if (!MOReg) in rescheduleMIBelowKill()
920 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) || in rescheduleMIBelowKill()
1043 if (!MOReg) in rescheduleKillAboveMI()
1050 Uses.push_back(MOReg); in rescheduleKillAboveMI()
1054 Defs.push_back(MOReg); in rescheduleKillAboveMI()
1079 if (!MOReg) in rescheduleKillAboveMI()
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H A DDetectDeadLanes.cpp191 Register MOReg = MO.getReg(); in addUsedLanesOnOperand() local
192 if (!Register::isVirtualRegister(MOReg)) in addUsedLanesOnOperand()
198 UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg); in addUsedLanesOnOperand()
200 unsigned MORegIdx = Register::virtReg2Index(MOReg); in addUsedLanesOnOperand()
374 Register MOReg = MO.getReg(); in determineInitialDefinedLanes() local
375 if (!MOReg) in determineInitialDefinedLanes()
379 if (Register::isPhysicalRegister(MOReg)) { in determineInitialDefinedLanes()
384 assert(Register::isVirtualRegister(MOReg)); in determineInitialDefinedLanes()
385 if (MRI->hasOneDef(MOReg)) { in determineInitialDefinedLanes()
479 Register MOReg = MO.getReg(); in isUndefInput() local
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H A DLiveVariables.cpp519 Register MOReg = MO.getReg(); in runOnInstr() local
521 if (!(Register::isPhysicalRegister(MOReg) && MRI->isReserved(MOReg))) in runOnInstr()
524 UseRegs.push_back(MOReg); in runOnInstr()
529 if (Register::isPhysicalRegister(MOReg) && !MRI->isReserved(MOReg)) in runOnInstr()
531 DefRegs.push_back(MOReg); in runOnInstr()
537 for (unsigned MOReg : UseRegs) { in runOnInstr() local
540 else if (!MRI->isReserved(MOReg)) in runOnInstr()
541 HandlePhysRegUse(MOReg, MI); in runOnInstr()
549 for (unsigned MOReg : DefRegs) { in runOnInstr() local
551 HandleVirtRegDef(MOReg, MI); in runOnInstr()
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H A DMachineInstrBundle.cpp330 Register MOReg = MO.getReg(); in AnalyzePhysRegInBundle() local
331 if (!MOReg || !Register::isPhysicalRegister(MOReg)) in AnalyzePhysRegInBundle()
334 if (!TRI->regsOverlap(MOReg, Reg)) in AnalyzePhysRegInBundle()
337 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in AnalyzePhysRegInBundle()
H A DMachineInstr.cpp951 Register MOReg = MO.getReg(); in findRegisterUseOperandIdx() local
952 if (!MOReg) in findRegisterUseOperandIdx()
954 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) in findRegisterUseOperandIdx()
1005 Register MOReg = MO.getReg(); in findRegisterDefOperandIdx() local
1006 bool Found = (MOReg == Reg); in findRegisterDefOperandIdx()
1009 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx()
1011 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx()
1913 Register MOReg = MO.getReg(); in addRegisterDead() local
1914 if (!MOReg) in addRegisterDead()
1917 if (MOReg == Reg) { in addRegisterDead()
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H A DTargetInstrInfo.cpp1280 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs() local
1281 if (MOReg.isUndef()) in getRegSequenceInputs()
1287 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
1305 const MachineOperand &MOReg = MI.getOperand(1); in getExtractSubregInputs() local
1306 if (MOReg.isUndef()) in getExtractSubregInputs()
1312 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
1313 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
H A DMachineCSE.cpp386 Register MOReg = MO.getReg(); in PhysRegDefsReach() local
387 if (Register::isVirtualRegister(MOReg)) in PhysRegDefsReach()
389 if (PhysRefs.count(MOReg.asMCReg())) in PhysRegDefsReach()
H A DMachineLICM.cpp1064 Register MOReg = MO.getReg(); in HasHighOperandLatency() local
1065 if (MOReg != Reg) in HasHighOperandLatency()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp581 Register MOReg = MO.getReg(); in restoreLatency() local
583 IsSameOrSubReg = (MOReg == DepR); in restoreLatency()
585 IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg); in restoreLatency()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp149 if (Register MOReg = MO.getReg()) { in getRegReferences() local
150 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp5444 const MachineOperand *MOReg = &MI.getOperand(1); in getRegSequenceLikeInputs() local
5445 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5446 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5447 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5449 MOReg = &MI.getOperand(2); in getRegSequenceLikeInputs()
5450 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5451 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5470 const MachineOperand &MOReg = MI.getOperand(2); in getExtractSubregLikeInputs() local
5471 if (MOReg.isUndef()) in getExtractSubregLikeInputs()
5473 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
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