| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 110 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
149 setOperationAction(ISD::MLOAD, P, Custom); in initializeHVXLowering()
191 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
258 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
1967 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
1969 if (Opc == ISD::MLOAD) { in LowerHvxMaskedOp()
2175 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
2182 if (MemOpc == ISD::MLOAD) { in SplitHvxMemOp()
2400 case ISD::MLOAD: in LowerHvxOperation()
2466 case ISD::MLOAD: in LowerHvxOperation()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 64 case ISD::MLOAD: in getVVPOpcode()
205 case ISD::MLOAD: in getMaskPos()
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| H A D | VEISelLowering.cpp | 335 for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE}) in initVPUActions()
1929 case ISD::MLOAD: in LowerOperation()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1207 MLOAD, enumerator
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| H A D | SelectionDAGNodes.h | 1411 case ISD::MLOAD:
2609 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2612 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2628 return N->getOpcode() == ISD::MLOAD ||
2641 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2656 return N->getOpcode() == ISD::MLOAD;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 395 case ISD::MLOAD: return "masked_load"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 75 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N)); in PromoteIntegerResult()
1658 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N), in PromoteIntegerOperand()
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| H A D | LegalizeVectorTypes.cpp | 978 case ISD::MLOAD: in SplitVectorResult()
3686 case ISD::MLOAD: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 771 case ISD::MLOAD: { in AddNodeIDCustom()
8628 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
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| H A D | DAGCombiner.cpp | 1791 case ISD::MLOAD: return visitMLOAD(N); in visit()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 595 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
690 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
818 {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); in RISCVTargetLowering()
889 setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE, in RISCVTargetLowering()
3504 case ISD::MLOAD: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1160 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1246 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1292 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1353 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1669 setOperationAction(ISD::MLOAD, VT, Custom); in addTypeForFixedLengthSVE()
5577 case ISD::MLOAD: in LowerOperation()
16750 return OC == ISD::LOAD || OC == ISD::MLOAD || in isCheapToExtend()
17236 if (N->getOperand(0).getOpcode() == ISD::MLOAD && in performUnpackCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1448 case ISD::MLOAD: in SelectT2AddrModeImm7Offset()
3999 case ISD::MLOAD: in Select()
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| H A D | ARMISelLowering.cpp | 264 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
338 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
10423 case ISD::MLOAD: in LowerOperation()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 666 def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1517 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
1723 setOperationAction(ISD::MLOAD, VT, Custom); in X86TargetLowering()
1890 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1897 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
2017 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2350 ISD::MLOAD, in X86TargetLowering()
32349 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG); in LowerOperation()
55063 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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