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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.ds.fmax.ll31 ; GFX8-MIR-NEXT: {{ $}}
43 ; GFX9-MIR-NEXT: {{ $}}
75 ; GFX8-MIR-NEXT: {{ $}}
87 ; GFX9-MIR-NEXT: {{ $}}
118 ; GFX8-MIR-NEXT: {{ $}}
129 ; GFX9-MIR-NEXT: {{ $}}
158 ; GFX8-MIR-NEXT: {{ $}}
169 ; GFX9-MIR-NEXT: {{ $}}
199 ; GFX8-MIR-NEXT: {{ $}}
209 ; GFX9-MIR-NEXT: {{ $}}
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-this-return.ll21 ; GISEL-MIR-LABEL: name: C_ctor_base
22 ; GISEL-MIR: bb.1.entry:
23 ; GISEL-MIR: liveins: $w1, $x0
49 ; GISEL-MIR: bb.1.entry:
50 ; GISEL-MIR: liveins: $w1, $x0
81 ; GISEL-MIR: bb.1.entry:
82 ; GISEL-MIR: liveins: $w1, $x0
97 ; GISEL-MIR: bb.1.entry:
98 ; GISEL-MIR: liveins: $w1, $x0
118 ; GISEL-MIR: bb.1.entry:
[all …]
H A Dmerge-scoped-aa-store.ll5 ; MIR-DAG: ![[DOMAIN:[0-9]+]] = distinct !{!{{[0-9]+}}, !"domain"}
10 ; MIR-DAG: ![[SET0:[0-9]+]] = !{![[SCOPE0]]}
11 ; MIR-DAG: ![[SET1:[0-9]+]] = !{![[SCOPE1]]}
12 ; MIR-DAG: ![[SET2:[0-9]+]] = !{![[SCOPE2]]}
13 ; MIR-DAG: ![[SET3:[0-9]+]] = !{![[SCOPE3]]}
16 ; MIR-LABEL: name: blam0
32 ; MIR-LABEL: name: blam1
33 ; MIR: machineMetadataNodes:
34 ; MIR-DAG: ![[MMSET0:[0-9]+]] = !{![[SCOPE2]], ![[SCOPE1]]}
35 ; MIR-DAG: ![[MMSET1:[0-9]+]] = !{}
[all …]
H A Dmemcpy-scoped-aa.ll5 ; MIR-DAG: ![[DOMAIN:[0-9]+]] = distinct !{!{{[0-9]+}}, !"bax"}
6 ; MIR-DAG: ![[SCOPE0:[0-9]+]] = distinct !{!{{[0-9]+}}, ![[DOMAIN]], !"bax: %p"}
7 ; MIR-DAG: ![[SCOPE1:[0-9]+]] = distinct !{!{{[0-9]+}}, ![[DOMAIN]], !"bax: %q"}
8 ; MIR-DAG: ![[SET0:[0-9]+]] = !{![[SCOPE0]]}
9 ; MIR-DAG: ![[SET1:[0-9]+]] = !{![[SCOPE1]]}
11 ; MIR-LABEL: name: test_memcpy
34 ; MIR-LABEL: name: test_memcpy_inline
57 ; MIR-LABEL: name: test_memmove
80 ; MIR-LABEL: name: test_memset
81 ; MIR: %2:gpr64 = MOVi64imm -6148914691236517206
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dproxy-reg-erasure-mir.ll2 ; RUN: | FileCheck %s --check-prefix=MIR --check-prefix=MIR-BEFORE
5 ; RUN: | FileCheck %s --check-prefix=MIR --check-prefix=MIR-AFTER
7 ; Check ProxyRegErasure pass MIR manipulation.
11 ; MIR: body:
12 ; MIR-DAG: Callseq_Start {{[0-9]+}}, {{[0-9]+}}
14 ; MIR-DAG: Callseq_End {{[0-9]+}}
16 ; MIR-BEFORE-DAG: %4:int32regs = ProxyRegI32 killed %0
17 ; MIR-BEFORE-DAG: %5:int32regs = ProxyRegI32 killed %1
18 ; MIR-BEFORE-DAG: %6:int32regs = ProxyRegI32 killed %2
19 ; MIR-BEFORE-DAG: %7:int32regs = ProxyRegI32 killed %3
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SparseTensor/
H A Dsparse_perm_lower.mlir4 // RUN: FileCheck %s --check-prefix=CHECK-MIR
51 // CHECK-MIR-LABEL: func @sparse_dynamic_dims(
52 // CHECK-MIR-SAME: %[[VAL_0:.*]]: !llvm.ptr<i8>,
72 // CHECK-MIR: scf.yield %[[VAL_26]] : f32
73 // CHECK-MIR: }
74 // CHECK-MIR: scf.yield %[[VAL_20]] : f32
75 // CHECK-MIR: }
76 // CHECK-MIR: scf.yield %[[VAL_15]] : f32
77 // CHECK-MIR: }
80 // CHECK-MIR: return %[[VAL_30]] : tensor<f32>
[all …]
H A Dsparse_lower_inplace.mlir4 // RUN: FileCheck %s --check-prefix=CHECK-MIR
54 // CHECK-MIR-LABEL: func @matvec(
55 // CHECK-MIR-SAME: %[[VAL_0:.*]]: !llvm.ptr<i8>,
56 // CHECK-MIR-SAME: %[[VAL_1:.*]]: tensor<64xf64>,
59 // CHECK-MIR-DAG: %[[VAL_4:.*]] = arith.constant 0 : index
60 // CHECK-MIR-DAG: %[[VAL_5:.*]] = arith.constant 1 : index
77 // CHECK-MIR: scf.yield %[[VAL_23]] : f64
78 // CHECK-MIR: }
80 // CHECK-MIR: }
82 // CHECK-MIR: return %[[VAL_25]] : tensor<32xf64>
[all …]
H A Dsparse_lower.mlir4 // RUN: FileCheck %s --check-prefix=CHECK-MIR
54 // CHECK-MIR-LABEL: func @matvec(
55 // CHECK-MIR-SAME: %[[VAL_0:.*]]: !llvm.ptr<i8>,
56 // CHECK-MIR-SAME: %[[VAL_1:.*]]: tensor<64xf64>,
59 // CHECK-MIR-DAG: %[[VAL_4:.*]] = arith.constant 0 : index
60 // CHECK-MIR-DAG: %[[VAL_5:.*]] = arith.constant 1 : index
77 // CHECK-MIR: scf.yield %[[VAL_26]] : f64
78 // CHECK-MIR: }
80 // CHECK-MIR: }
82 // CHECK-MIR: return %[[VAL_28]] : tensor<32xf64>
[all …]
H A Dsparse_lower_col.mlir4 // RUN: FileCheck %s --check-prefix=CHECK-MIR
56 // CHECK-MIR-LABEL: func @matvec(
57 // CHECK-MIR-SAME: %[[VAL_0:.*]]: !llvm.ptr<i8>,
58 // CHECK-MIR-SAME: %[[VAL_1:.*]]: tensor<64xf64>,
60 // CHECK-MIR-DAG: %[[VAL_3:.*]] = arith.constant 64 : index
61 // CHECK-MIR-DAG: %[[VAL_5:.*]] = arith.constant 0 : index
62 // CHECK-MIR-DAG: %[[VAL_6:.*]] = arith.constant 1 : index
80 // CHECK-MIR: }
81 // CHECK-MIR: }
83 // CHECK-MIR: return %[[VAL_26]] : tensor<32xf64>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmemcpy-scoped-aa.ll7 ; MIR-DAG: ![[DOMAIN:[0-9]+]] = distinct !{!{{[0-9]+}}, !"bax"}
8 ; MIR-DAG: ![[SCOPE0:[0-9]+]] = distinct !{!{{[0-9]+}}, ![[DOMAIN]], !"bax: %p"}
9 ; MIR-DAG: ![[SCOPE1:[0-9]+]] = distinct !{!{{[0-9]+}}, ![[DOMAIN]], !"bax: %q"}
10 ; MIR-DAG: ![[SET0:[0-9]+]] = !{![[SCOPE0]]}
11 ; MIR-DAG: ![[SET1:[0-9]+]] = !{![[SCOPE1]]}
13 ; MIR-LABEL: name: test_memcpy
30 ; MIR-LABEL: name: test_memcpy_inline
47 ; MIR-LABEL: name: test_memmove
64 ; MIR-LABEL: name: test_memset
65 ; MIR: %2:gr64 = MOV64ri -6148914691236517206
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-lower-constant-pool-index.ll3 ; RUN: --check-prefix=32SMALL-MIR %s
7 ; RUN: --check-prefix=32LARGE-MIR %s
11 ; RUN: --check-prefix=64SMALL-MIR %s
15 ; RUN: --check-prefix=64LARGE-MIR %s
34 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc %const.0, $r2 :: (load (s32) from got)
35 ; 32SMALL-MIR: renamable $f[[REG2:[0-9]+]] = LFS 0, killed renamable $r[[REG1]] :: (load (s32) from…
37 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, %const.0
39 ; 32LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $r[[REG2]] :: (load (s32) from…
41 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocCPT %const.0, $x2 :: (load (s64) from got)
42 ; 64SMALL-MIR: renamable $f[[REG2:[0-9]+]] = LFS 0, killed renamable $x[[REG1]] :: (load (s32) from…
[all …]
H A Daix-lower-jump-table.ll3 ; RUN: --check-prefix=32SMALL-MIR %s
7 ; RUN: --check-prefix=32LARGE-MIR %s
11 ; RUN: --check-prefix=64SMALL-MIR %s
15 ; RUN: --check-prefix=64LARGE-MIR %s
65 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc %jump-table.0, $r2 :: (load (s32) from got)
66 ; 32SMALL-MIR: renamable $r[[REG3:[0-9]+]] = RLWINM killed renamable $r[[REG2:[0-9]+]], 2, 0, 29
70 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, %jump-table.0
72 ; 32LARGE-MIR: renamable $r[[REG4:[0-9]+]] = RLWINM killed renamable $r[[REG3:[0-9]+]], 2, 0, 29
77 ; 64SMALL-MIR: renamable $x[[REG3:[0-9]+]] = RLDIC killed renamable $x[[REG2:[0-9]+]], 2, 30
81 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %jump-table.0
[all …]
H A Daix-lower-block-address.ll3 ; RUN: --check-prefix=32SMALL-MIR %s
7 ; RUN: --check-prefix=32LARGE-MIR %s
11 ; RUN: --check-prefix=64SMALL-MIR %s
15 ; RUN: --check-prefix=64LARGE-MIR %s
39 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc blockaddress(@foo, %ir-block.__here), $r2 :: (l…
41 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, blockaddress(@foo, %ir-block.__here)
42 ; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL blockaddress(@foo, %ir-block.__here), killed r…
44 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocBA blockaddress(@foo, %ir-block.__here), $x2 :: (…
46 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, blockaddress(@foo, %ir-block.__here)
47 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL blockaddress(@foo, %ir-block.__here), killed re…
H A Daix-sret-param.ll3 ; RUN: --check-prefixes=MIR,MIR32 %s
7 ; RUN: --check-prefixes=MIR,MIR64 %s
35 ; MIR: name: test1
36 ; MIR: stack:
37 ; MIR-NEXT: - { id: 0, name: s, type: default, offset: 0, size: 1, alignment: 8,
68 ; MIR: name: test2
69 ; MIR: stack:
70 ; MIR-NEXT: - { id: 0, name: t, type: default, offset: 0, size: 24, alignment: 8,
H A Dfp-strict-conv.ll332 ; MIR-LABEL: name: fptoint_nofpexcept_f64
350 ; MIR-LABEL: name: fptoint_nofpexcept_f32
368 ; MIR-LABEL: name: inttofp_nofpexcept_i32
369 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDSP
370 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDSP
371 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDDP
372 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDDP
386 ; MIR-LABEL: name: inttofp_nofpexcept_i64
387 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDSP
388 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDSP
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.ds.gws.barrier-fastregalloc.ll2 …er=postrapseudos -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=MIR %s
5 ; MIR-LABEL: name: gws_barrier_offset0{{$}}
6 ; MIR: BUNDLE implicit{{( killed)?( renamable)?}} $vgpr0, implicit $m0, implicit $exec {
7 ; MIR-NEXT: DS_GWS_BARRIER renamable $vgpr0, 0, implicit $m0, implicit $exec :: (load (s32) from cu…
8 ; MIR-NEXT: S_WAITCNT 0
9 ; MIR-NEXT: }
H A Dmemcpy-scoped-aa.ll2 …amdgcn-amd-amdhsa -mcpu=gfx1010 -stop-after=finalize-isel -o - %s | FileCheck --check-prefix=MIR %s
8 ; MIR-DAG: ![[DOMAIN:[0-9]+]] = distinct !{!{{[0-9]+}}, !"bax"}
9 ; MIR-DAG: ![[SCOPE0:[0-9]+]] = distinct !{!{{[0-9]+}}, ![[DOMAIN]], !"bax: %p"}
10 ; MIR-DAG: ![[SCOPE1:[0-9]+]] = distinct !{!{{[0-9]+}}, ![[DOMAIN]], !"bax: %q"}
11 ; MIR-DAG: ![[SET0:[0-9]+]] = !{![[SCOPE0]]}
12 ; MIR-DAG: ![[SET1:[0-9]+]] = !{![[SCOPE1]]}
14 ; MIR-LABEL: name: test_memcpy
16 ; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) int…
36 ; MIR-LABEL: name: test_memcpy_inline
58 ; MIR-LABEL: name: test_memmove
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SampleProfile/
H A Dpseudo-probe-selectionDAG.ll4 ; RUN: llc -mtriple=x86_64-- -stop-after=finalize-isel %t -o - | FileCheck %s --check-prefix=MIR
22 ; MIR-label: bb.1.if.end
23 ; MIR: %[[#REG:]]:gr64 = IMPLICIT_DEF
24 ; MIR: TEST8mi killed %[[#REG]], 1, $noreg, 0, $noreg, 16
25 ; MIR: JCC_1
H A Dpseudo-probe-emit.ll4 ; RUN: llc %t -stop-after=pseudo-probe-inserter -o - | FileCheck %s --check-prefix=CHECK-MIR
20 ; CHECK-MIR: PSEUDO_PROBE [[#GUID:]], 1, 0, 0
26 ; CHECK-MIR: PSEUDO_PROBE [[#GUID]], 3, 0, 0
27 ; CHECK-MIR: PSEUDO_PROBE [[#GUID]], 4, 0, 0
35 ; CHECK-MIR: PSEUDO_PROBE [[#GUID]], 2, 0, 0
36 ; CHECK-MIR: PSEUDO_PROBE [[#GUID]], 4, 0, 0
52 ; CHECK-MIR: PSEUDO_PROBE [[#GUID2:]], 1, 0, 0
56 ; CHECK-MIR: PSEUDO_PROBE [[#GUID2]], 2, 1, 0
61 ; CHECK-MIR: PSEUDO_PROBE [[#GUID2]], 3, 2, 0
H A Dpseudo-probe-dangle.ll6 ; RUN: llc -stop-after=tailduplication <%t1 | FileCheck %s --check-prefix=MIR-tail
36 ; MIR-tail: bb.0
37 ; MIR-tail: PSEUDO_PROBE [[#GUID:]], 1, 0, 0
38 ; MIR-tail-NOT: PSEUDO_PROBE [[#GUID:]], 2
39 ; MIR-tail-NOT: PSEUDO_PROBE [[#GUID:]], 3
40 ; MIR-tail: PSEUDO_PROBE [[#GUID:]], 4, 0, 0
/llvm-project-15.0.7/llvm/unittests/Target/WebAssembly/
H A DWebAssemblyExceptionInfoTest.cpp43 std::unique_ptr<MIRParser> &MIR, in parseMIR() argument
48 MIR = createMIRParser(std::move(MBuffer), Context); in parseMIR()
49 if (!MIR) in parseMIR()
52 std::unique_ptr<Module> M = MIR->parseIRModule(); in parseMIR()
58 if (MIR->parseMachineFunctions(*M, MMI)) in parseMIR()
157 std::unique_ptr<MIRParser> MIR; in TEST() local
160 parseMIR(Context, MIR, *TM, MIRString, "test0", MMI); in TEST()
332 std::unique_ptr<MIRParser> MIR; in TEST() local
335 parseMIR(Context, MIR, *TM, MIRString, "test1", MMI); in TEST()
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DGISelMITest.h57 std::unique_ptr<MIRParser> &MIR, in parseMIR() argument
63 MIR = createMIRParser(std::move(MBuffer), Context); in parseMIR()
64 if (!MIR) in parseMIR()
67 std::unique_ptr<Module> M = MIR->parseIRModule(); in parseMIR()
73 if (MIR->parseMachineFunctions(*M, MMI)) in parseMIR()
81 std::unique_ptr<MIRParser> MIR; in createDummyModule() local
84 parseMIR(Context, MIR, TM, MIRString, FuncName, *MMI); in createDummyModule()
/llvm-project-15.0.7/llvm/utils/vim/syntax/
H A Dmir.vim14 " MIR is embedded in a yaml container, so we load all of the yaml syntax.
24 " The `body:` field of a document contains the MIR dump of the function
25 syntax include @MIR syntax/machine-ir.vim
26 syntax region mir start=/\(^body:\s*|\)\@<=/ end=/\(^[^[:space:]]\)\@=/ contains=@MIR
/llvm-project-15.0.7/llvm/docs/
H A DMIRLangRef.rst2 Machine IR (MIR) Format Reference Manual
14 This document is a reference manual for the Machine IR (MIR) serialization
15 format. MIR is a human readable serialization format that is used to represent
19 The MIR serialization format is designed to be used for testing the code
25 The MIR serialization format uses a YAML container. YAML is a standard
36 MIR Testing Guide
39 You can use the MIR format for testing in two different ways:
45 tests and check the MIR output of a specific code generation pass.
53 resulting MIR code.
80 Simplifying MIR files
[all …]
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DPipeline.rst22 Converts :doc:`LLVM-IR <../LangRef>` into :doc:`gMIR (Generic MIR) <GMIR>`.
24 It's somewhat analogous to SelectionDAGBuilder but builds a flavour of MIR
26 same data structures as MIR but has more relaxed constraints. For example,
35 can shape the MIR as they wish.
40 cross-register-bank copies by clustering portions of the MIR together.
45 constrained enough that it becomes MIR.
56 The representation must be gMIR, MIR, or a mixture of the two after this pass.
58 gradually transition the gMIR to MIR.
71 have completed the conversion from gMIR to MIR.
135 and perform a single step of the algorithm and check the result. The MIR and

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