Home
last modified time | relevance | path

Searched refs:MI2 (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp403 if (!GetImm(MI2, 2, Offset2)) in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
465 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
622 MachineInstr *MI2 = &*NextMII; in ReduceMoveToMovep() local
633 if (MI2->getOpcode() != Entry.WideOpc()) in ReduceMoveToMovep()
738 MIB.add(MI2->getOperand(0)); in ReplaceInstruction()
741 MIB.add(MI2->getOperand(1)); in ReplaceInstruction()
745 MIB.add(MI2->getOperand(0)); in ReplaceInstruction()
747 MIB.add(MI2->getOperand(1)); in ReplaceInstruction()
751 MIB.add(MI2->getOperand(2)); in ReplaceInstruction()
[all …]
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DMachineInstrTest.cpp68 auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc()); in TEST() local
69 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
70 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); in TEST()
74 ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs)); in TEST()
75 ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs)); in TEST()
77 ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs)); in TEST()
78 ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs)); in TEST()
102 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { in checkHashAndIsEqualMatch() argument
103 bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2); in checkHashAndIsEqualMatch()
104 bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1); in checkHashAndIsEqualMatch()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp461 MachineInstr *MI2 = nullptr; in eliminateTruncSeq() local
480 MI2 = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
483 if (!MI2 || in eliminateTruncSeq()
484 MI2->getOpcode() != BPF::SLL_ri || in eliminateTruncSeq()
485 MI2->getOperand(2).getImm() != 32) in eliminateTruncSeq()
489 SrcReg = MI2->getOperand(1).getReg(); in eliminateTruncSeq()
540 if (MI2) in eliminateTruncSeq()
541 MI2->eraseFromParent(); in eliminateTruncSeq()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp439 MachineInstr *MI2 = *I2; in hoistAndMergeSGPRInits() local
474 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
475 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
478 << printMBBReference(*MI2->getParent()) << " " << *MI2); in hoistAndMergeSGPRInits()
479 MergedInstrs.insert(MI2); in hoistAndMergeSGPRInits()
484 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
485 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
496 MI2->getParent()); in hoistAndMergeSGPRInits()
503 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
508 << printMBBReference(*MI2->getParent()) << " to " in hoistAndMergeSGPRInits()
[all …]
H A DSIInstrInfo.cpp455 const MachineInstr &MI2, in memOpsHaveSameBasePtr() argument
463 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
467 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr()
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/NativePDB/
H A Dast-types.cpp93 class MI2 : MI { int mi2; }; class
100 typedef void (MI2::*MI2TYPE)();
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp302 const MachineInstr &MI2, in alias() argument
304 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias()
H A DTargetInstrInfo.cpp707 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
711 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
714 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
722 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
727 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
729 std::swap(MI1, MI2); in hasReassociableSibling()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp289 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply() local
290 if (!QII->isHVXVec(MI2)) in apply()
292 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply()
H A DHexagonVLIWPacketizer.h144 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
H A DHexagonInstrInfo.h406 const MachineInstr &MI2) const;
418 const MachineInstr &MI2) const;
H A DHexagonVLIWPacketizer.cpp967 MachineInstr &MI2) { in arePredicatesComplements() argument
971 getPredicateSense(MI2, HII) == PK_Unknown) in arePredicatesComplements()
1024 unsigned PReg2 = getPredicatedRegister(MI2, HII); in arePredicatesComplements()
1028 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1029 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
H A DHexagonInstrInfo.cpp2677 const MachineInstr &MI2) const { in isToBeScheduledASAP()
2681 int N = MI2.getNumOperands(); in isToBeScheduledASAP()
2683 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg()) in isToBeScheduledASAP()
2686 if (mayBeNewStore(MI2)) in isToBeScheduledASAP()
2687 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi) in isToBeScheduledASAP()
2688 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2689 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3025 const MachineInstr &MI2) const { in addLatencyToSchedule()
3026 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
3027 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
H A DHexagonPatterns.td814 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
816 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
/llvm-project-15.0.7/clang/test/Analysis/
H A Dpadding_cpp.cpp102 class MI2 : public PaddedA, public InnerPaddedB { // xxxexpected-warning{{Excessive padding in 'cla… class
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLoadStoreOpt.h49 bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DDFAPacketizer.h189 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp278 const MachineInstr &MI2, unsigned N2) const;
401 const MachineInstr &MI2, in getAddrDispShift() argument
404 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
H A DX86ISelLowering.h1679 MachineInstr &MI2,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp314 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
318 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp104 const MachineInstr &MI2, in aliasIsKnownForLoadStore() argument
108 auto *LdSt2 = dyn_cast<GLoadStore>(&MI2); in aliasIsKnownForLoadStore()
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/bugprone/
H A Deasily-swappable-parameters-len2.cpp148 void typedefChain(int I, MyInt1 MI1, MyInt2 MI2, MyInt2b MI2b) {} in typedefChain() argument
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp1515 auto MI2 = in expandLSLW4Rd() local
1521 MI2->getOperand(3).setIsDead(); in expandLSLW4Rd()
1713 auto MI2 = in expandLSRW4Rd() local
1719 MI2->getOperand(3).setIsDead(); in expandLSRW4Rd()