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Searched refs:Lowering (Results 1 – 25 of 36) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/LTO/
H A DUpdateCompilerUsed.cpp75 const TargetLowering *Lowering = in initializeLibCalls() local
78 if (Lowering && TLSet.insert(Lowering).second) in initializeLibCalls()
84 Lowering->getLibcallName(static_cast<RTLIB::Libcall>(I))) in initializeLibCalls()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86DynAllocaExpander.cpp44 enum Lowering { TouchAndSub, Sub, Probe }; enum in __anon2977b71f0111::X86DynAllocaExpander
47 typedef MapVector<MachineInstr*, Lowering> LoweringMap;
53 Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
56 void lower(MachineInstr* MI, Lowering L);
96 X86DynAllocaExpander::Lowering
160 Lowering L = getLowering(Offset, Amount); in computeLowerings()
198 void X86DynAllocaExpander::lower(MachineInstr *MI, Lowering L) { in lower()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A DO0-pipeline.ll20 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
25 ; CHECK-NEXT: Shadow Stack GC Lowering
H A DO3-pipeline.ll23 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
46 ; CHECK-NEXT: Shadow Stack GC Lowering
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A DO0-pipeline.ll16 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
21 ; CHECK-NEXT: Shadow Stack GC Lowering
H A DO3-pipeline.ll19 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
62 ; CHECK-NEXT: Shadow Stack GC Lowering
H A Dmul_pow2.ll8 ; Lowering other positive constants are not supported yet.
459 ; Lowering other negative constants are not supported yet.
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A DO0-pipeline.ll18 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
25 ; CHECK-NEXT: Shadow Stack GC Lowering
H A Dopt-pipeline.ll27 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
50 ; CHECK-NEXT: Shadow Stack GC Lowering
/llvm-project-15.0.7/mlir/docs/Tutorials/Toy/
H A D_index.md33 - [Chapter #6](Ch-6.md): Lowering to LLVM and code generation. Here we'll
H A DCh-6.md1 # Chapter 6: Lowering to LLVM and CodeGeneration
10 ## Lowering to LLVM
108 ### Full Lowering
H A DCh-5.md1 # Chapter 5: Partial Lowering to Lower-Level Dialects for Optimization
161 ## Partial Lowering
180 ### Design Considerations With Partial Lowering argument
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp414 const SITargetLowering& Lowering = in glueCopyToM0() local
419 SDValue M0 = Lowering.copyToM0(*CurDAG, N->getOperand(0), SDLoc(N), Val); in glueCopyToM0()
663 const SITargetLowering& Lowering = in Select() local
665 N = Lowering.legalizeTargetIndependentNode(N, *CurDAG); in Select()
1351 const SITargetLowering& Lowering = in SelectMUBUFAddr64() local
1354 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1508 const SITargetLowering& Lowering = in SelectMUBUFOffset() local
1511 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
2980 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG() local
2994 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG); in PostprocessISelDAG()
H A DAMDGPUInstructions.td203 const SITargetLowering &Lowering =
206 return Lowering.isCanonicalized(*CurDAG, N->getOperand(0)) &&
207 Lowering.isCanonicalized(*CurDAG, N->getOperand(1));
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A DO3-pipeline.ll6 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
30 ; CHECK-NEXT: Shadow Stack GC Lowering
H A Dvector-DAGCombine.ll319 ; Lowering to build vector was breaking the single use property of the load of
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A DO3-pipeline.ll19 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
54 ; CHECK-NEXT: Shadow Stack GC Lowering
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrPatternsVec.td32 // Custom Lowering is used for other load/store instructions.
/llvm-project-15.0.7/llvm/docs/
H A DCoroutines.rst65 Switched-Resume Lowering
126 Returned-Continuation Lowering
177 Async Lowering
228 `llvm.coro.id.async` intrinsic. Lowering will update the size entry with the
240 Lowering will split an async coroutine into a ramp function and one resume
1225 from the frontend. Lowering will add to this size the size required by the frame
1235 Lowering will update the context size requirement in this struct by adding the
1616 Lowering will replace this intrinsic with the resume function for this suspend
1624 suspend point. It should take 3 arguments. Lowering will `musttail` call this
1654 Lowering will replace this intrinsic with its coroutine function argument.
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Ddebuginfo.ll50 ; Lowering dbg.declare in instcombine doesn't handle this case very well.
/llvm-project-15.0.7/mlir/docs/Dialects/
H A DVector.md154 ### Virtual Vector to Hardware Vector Lowering
271 ### Alternatives For Lowering an n-D Vector Type to LLVM
274 `vector<s_0x...s_{n-1}xf32>`). Lowering such an `n-D` MLIR vector type to an
431 #### Implication on Lowering to Accelerators
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DLegalizer.rst321 * Lowering them to G_TRUNC+G_ANYEXT and some legalizable instructions.
322 * Lowering them to target instructions which are legal by definition.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllc-pipeline.ll28 ; GCN-O0-NEXT: Pre-ISel Intrinsic Lowering
163 ; GCN-O1-NEXT: Pre-ISel Intrinsic Lowering
420 ; GCN-O1-OPTS-NEXT: Pre-ISel Intrinsic Lowering
710 ; GCN-O2-NEXT: Pre-ISel Intrinsic Lowering
1003 ; GCN-O3-NEXT: Pre-ISel Intrinsic Lowering
/llvm-project-15.0.7/mlir/docs/Rationale/
H A DRationaleLinalgDialect.md482 #### Progressive Lowering: Don't Lose Information too Quickly<a name="#progressive_lowering"></a>
484 Lowering too quickly to affine, generic loops or CFG form reduces the
605 [Progressive Lowering](#progressive_lowering), closed-ness under
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transfer-to-vector-load-store.mlir194 // Lowering of transfer_read with broadcasting is supported (note that a `load`

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