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Searched refs:LogicOp (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp909 struct LogicOp { struct
910 LogicOp() = default;
925 case SystemZ::NILMux: return LogicOp(32, 0, 16); in interpretAndImmediate()
926 case SystemZ::NIHMux: return LogicOp(32, 16, 16); in interpretAndImmediate()
927 case SystemZ::NILL64: return LogicOp(64, 0, 16); in interpretAndImmediate()
928 case SystemZ::NILH64: return LogicOp(64, 16, 16); in interpretAndImmediate()
929 case SystemZ::NIHL64: return LogicOp(64, 32, 16); in interpretAndImmediate()
930 case SystemZ::NIHH64: return LogicOp(64, 48, 16); in interpretAndImmediate()
931 case SystemZ::NIFMux: return LogicOp(32, 0, 32); in interpretAndImmediate()
932 case SystemZ::NILF64: return LogicOp(64, 0, 32); in interpretAndImmediate()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/X86/
H A Dshufflemask-undef.ll26 %struct.LogicOp = type { i16, i8, i8 }
51 …ArrayRange, %struct.FogMode, %struct.HintMode, %struct.LineMode, %struct.LogicOp, %struct.MaskMode…
H A Dshufflemask-undef-inseltpoison.ll26 %struct.LogicOp = type { i16, i8, i8 }
51 …ArrayRange, %struct.FogMode, %struct.HintMode, %struct.LineMode, %struct.LogicOp, %struct.MaskMode…
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2743 SDValue computeLogicOpInGPR(SDValue LogicOp);
2917 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { in computeLogicOpInGPR() argument
2918 assert(isLogicOp(LogicOp.getOpcode()) && in computeLogicOpInGPR()
2920 assert(LogicOp.getValueType() == MVT::i1 && in computeLogicOpInGPR()
2922 SDLoc dl(LogicOp); in computeLogicOpInGPR()
2926 bool IsBitwiseNegation = isBitwiseNot(LogicOp); in computeLogicOpInGPR()
2947 LHS = getLogicOperand(LogicOp.getOperand(0)); in computeLogicOpInGPR()
2948 RHS = getLogicOperand(LogicOp.getOperand(1)); in computeLogicOpInGPR()
2965 switch (LogicOp.getOpcode()) { in computeLogicOpInGPR()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp8261 Instruction *LogicOp; in splitBranchCondition() local
8264 m_Br(m_OneUse(m_Instruction(LogicOp)), TBB, FBB))) in splitBranchCondition()
8277 if (match(LogicOp, in splitBranchCondition()
8280 else if (match(LogicOp, m_LogicalOr(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
8305 LogicOp->eraseFromParent(); in splitBranchCondition()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6111 if (LogicOp.getOpcode() != LogicOpcode || in foldLogicOfShifts()
6124 LogicOp.getOperand(0).getOperand(1) == Y) { in foldLogicOfShifts()
6125 X0 = LogicOp.getOperand(0).getOperand(0); in foldLogicOfShifts()
6126 Z = LogicOp.getOperand(1); in foldLogicOfShifts()
6129 X0 = LogicOp.getOperand(1).getOperand(0); in foldLogicOfShifts()
6130 Z = LogicOp.getOperand(0); in foldLogicOfShifts()
8623 SDValue LogicOp = Shift->getOperand(0); in combineShiftOfShiftedLogic() local
8624 if (!LogicOp.hasOneUse()) in combineShiftOfShiftedLogic()
8627 unsigned LogicOpcode = LogicOp.getOpcode(); in combineShiftOfShiftedLogic()
8667 Y = LogicOp.getOperand(1); in combineShiftOfShiftedLogic()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23231 unsigned LogicOp = IsFABS ? X86ISD::FAND : in LowerFABSorFNEG() local
23237 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
23242 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()