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Searched refs:LoadedVT (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1588 EVT LoadedVT = LD->getMemoryVT(); in tryARMIndexedLoad() local
1601 } else if (LoadedVT == MVT::i32 && in tryARMIndexedLoad()
1606 } else if (LoadedVT == MVT::i16 && in tryARMIndexedLoad()
1612 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { in tryARMIndexedLoad()
1663 EVT LoadedVT = LD->getMemoryVT(); in tryT1IndexedLoad() local
1694 EVT LoadedVT = LD->getMemoryVT(); in tryT2IndexedLoad() local
1740 EVT LoadedVT; in tryMVEIndexedLoad() local
1752 LoadedVT = LD->getMemoryVT(); in tryMVEIndexedLoad()
1753 if (!LoadedVT.isVector()) in tryMVEIndexedLoad()
1768 LoadedVT = LD->getMemoryVT(); in tryMVEIndexedLoad()
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/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp843 EVT LoadedVT = LD->getMemoryVT(); in tryLoad() local
850 if (!LoadedVT.isSimple()) in tryLoad()
885 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad()
894 assert(LoadedVT == MVT::v2f16 && "Unexpected vector type"); in tryLoad()
996 EVT LoadedVT = MemSD->getMemoryVT(); in tryLoadVector() local
998 if (!LoadedVT.isSimple()) in tryLoadVector()
1019 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp71 EVT LoadedVT = LD->getMemoryVT(); in SelectIndexedLoad() local
78 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc); in SelectIndexedLoad()
80 assert(LoadedVT.isSimple()); in SelectIndexedLoad()
81 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectIndexedLoad()
152 assert(LoadedVT.getSizeInBits() <= 32); in SelectIndexedLoad()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp271 EVT LoadedVT = LD->getMemoryVT(); in LegalizeOp() local
272 if (LoadedVT.isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
273 Action = TLI.getLoadExtAction(ExtType, LD->getValueType(0), LoadedVT); in LegalizeOp()
H A DTargetLowering.cpp8372 EVT LoadedVT = LD->getMemoryVT(); in expandUnalignedLoad() local
8377 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in expandUnalignedLoad()
8378 if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) { in expandUnalignedLoad()
8380 LoadedVT.isVector()) { in expandUnalignedLoad()
8389 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in expandUnalignedLoad()
8390 if (LoadedVT != VT) in expandUnalignedLoad()
8400 unsigned LoadedBytes = LoadedVT.getStoreSize(); in expandUnalignedLoad()
8405 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
8456 LoadedVT); in expandUnalignedLoad()
8462 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && in expandUnalignedLoad()
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H A DDAGCombiner.cpp5658 EVT LoadedVT = LoadN->getMemoryVT(); in isAndLoadExtLoad() local
5660 if (ExtVT == LoadedVT && in isAndLoadExtLoad()
5674 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5269 EVT LoadedVT = LD->getMemoryVT(); in Select() local
5288 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5289 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5300 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5301 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5325 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5326 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5337 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
5339 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()