Home
last modified time | relevance | path

Searched refs:Load2 (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.h430 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
448 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
H A DX86InstrInfo.cpp7139 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
7141 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
7144 unsigned Opc2 = Load2->getMachineOpcode(); in areLoadsFromSameBasePtr()
7314 return Load1->getOperand(I) == Load2->getOperand(I); in areLoadsFromSameBasePtr()
7328 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp)); in areLoadsFromSameBasePtr()
7337 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
7345 unsigned Opc2 = Load2->getMachineOpcode(); in shouldScheduleLoadsNear()
H A DX86ISelLowering.cpp48995 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr2, in combineLoad() local
49000 Load1.getValue(1), Load2.getValue(1)); in combineLoad()
49002 SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); in combineLoad()
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dmsan_kernel_basic.ll219 define i16 @Load2(i16* nocapture %p) nounwind uwtable sanitize_memory {
225 ; CHECK-LABEL: @Load2
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h246 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
257 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
H A DARMBaseInstrInfo.cpp1943 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1949 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
1973 switch (Load2->getMachineOpcode()) { in areLoadsFromSameBasePtr()
1994 if (Load1->getOperand(0) != Load2->getOperand(0) || in areLoadsFromSameBasePtr()
1995 Load1->getOperand(4) != Load2->getOperand(4)) in areLoadsFromSameBasePtr()
1999 if (Load1->getOperand(3) != Load2->getOperand(3)) in areLoadsFromSameBasePtr()
2004 isa<ConstantSDNode>(Load2->getOperand(1))) { in areLoadsFromSameBasePtr()
2006 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
2040 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && in shouldScheduleLoadsNear()
2042 Load2->getMachineOpcode() == ARM::t2LDRBi12) || in shouldScheduleLoadsNear()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1313 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1327 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h191 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp11302 LoadSDNode *Load2 = cast<LoadSDNode>(Op2); in tryToFoldExtendSelectLoad() local
11304 !TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load2->getMemoryVT())) in tryToFoldExtendSelectLoad()