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Searched refs:Load1 (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DAliasAnalysisTest.cpp180 auto *Load1 = new LoadInst(IntType, Addr, "load", BB); in TEST_F() local
198 EXPECT_EQ(AA.getModRefInfo(Load1, MemoryLocation()), ModRefInfo::Ref); in TEST_F()
199 EXPECT_EQ(AA.getModRefInfo(Load1, None), ModRefInfo::Ref); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.h430 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
448 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
H A DX86InstrInfo.cpp7139 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
7141 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
7143 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr()
7314 return Load1->getOperand(I) == Load2->getOperand(I); in areLoadsFromSameBasePtr()
7327 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp)); in areLoadsFromSameBasePtr()
7337 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
7344 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear()
7359 EVT VT = Load1->getValueType(0); in shouldScheduleLoadsNear()
H A DX86ISelLowering.cpp48991 SDValue Load1 = in combineLoad() local
49000 Load1.getValue(1), Load2.getValue(1)); in combineLoad()
49002 SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); in combineLoad()
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dmsan_kernel_basic.ll194 define i8 @Load1(i8* nocapture %p) nounwind uwtable sanitize_memory {
200 ; CHECK-LABEL: @Load1
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h246 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
257 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
H A DARMBaseInstrInfo.cpp1943 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1949 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
1952 switch (Load1->getMachineOpcode()) { in areLoadsFromSameBasePtr()
1994 if (Load1->getOperand(0) != Load2->getOperand(0) || in areLoadsFromSameBasePtr()
1995 Load1->getOperand(4) != Load2->getOperand(4)) in areLoadsFromSameBasePtr()
1999 if (Load1->getOperand(3) != Load2->getOperand(3)) in areLoadsFromSameBasePtr()
2003 if (isa<ConstantSDNode>(Load1->getOperand(1)) && in areLoadsFromSameBasePtr()
2005 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
2040 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && in shouldScheduleLoadsNear()
2041 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
[all …]
H A DARMISelLowering.cpp13415 LoadSDNode *Load1 = dyn_cast<LoadSDNode>(N1); in TryDistrubutionADDVecReduce() local
13416 if (!Load0 || !Load1 || Load0->getChain() != Load1->getChain() || in TryDistrubutionADDVecReduce()
13417 !Load0->isSimple() || !Load1->isSimple() || Load0->isIndexed() || in TryDistrubutionADDVecReduce()
13418 Load1->isIndexed()) in TryDistrubutionADDVecReduce()
13422 auto BaseLocDecomp1 = BaseIndexOffset::match(Load1, DAG); in TryDistrubutionADDVecReduce()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1313 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1327 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp175 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr() argument
178 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode()) in areLoadsFromSameBasePtr()
182 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr()
191 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1)) in areLoadsFromSameBasePtr()
195 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
224 if (NumOps != getNumOperandsNoGlue(Load1)) in areLoadsFromSameBasePtr()
228 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
233 if (NumOps == 5 && Load0->getOperand(1) != Load1->getOperand(1)) in areLoadsFromSameBasePtr()
239 dyn_cast<ConstantSDNode>(Load1->getOperand(NumOps - 3)); in areLoadsFromSameBasePtr()
255 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) in areLoadsFromSameBasePtr()
[all …]
H A DSIInstrInfo.h191 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
205 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2161 SDValue Load1 = DAG.getLoad(SingleTy, dl, Chain, Base1, MOp1); in SplitHvxMemOp() local
2163 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1), in SplitHvxMemOp()
2165 Load0.getValue(1), Load1.getValue(1)) }, dl); in SplitHvxMemOp()
H A DHexagonISelLowering.cpp3085 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO); in LowerUnalignedLoad() local
3088 {Load1, Load0, BaseNoOff.getOperand(0)}); in LowerUnalignedLoad()
3090 Load0.getValue(1), Load1.getValue(1)); in LowerUnalignedLoad()
/llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/
H A DDataFlowSanitizer.cpp2119 Value *Load1 = in loadShadowOriginSansLoadTracking() local
2121 return {combineShadows(Load, Load1, Pos), Origin}; in loadShadowOriginSansLoadTracking()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp11301 LoadSDNode *Load1 = cast<LoadSDNode>(Op1); in tryToFoldExtendSelectLoad() local
11303 if (!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load1->getMemoryVT()) || in tryToFoldExtendSelectLoad()