| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 873 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
883 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
1494 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>;
1498 (M2_mpy_up (LoReg $Rt), (LoReg $Rt)))>;
1602 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1604 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1611 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1649 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>;
1657 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32),
1737 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>;
[all …]
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| H A D | HexagonCopyToCombine.cpp | 756 Register LoReg = LoOperand.getReg(); in emitCombineIR() local
767 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
775 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
782 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
790 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
797 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
855 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
874 .addReg(LoReg, LoRegKillFlag); in emitCombineRR()
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| H A D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 1130 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
1132 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); in insertCFIInstructionsAt()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| H A D | AVRRegisterInfo.cpp | 285 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg, in splitReg() argument
289 LoReg = getSubReg(Reg, AVR::sub_lo); in splitReg()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1979 .addReg(LoReg, RegState::Implicit); in selectG_TRUNC()
2002 .addReg(LoReg) in selectG_TRUNC()
2235 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
2238 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg) in selectG_CONSTANT()
2245 .addReg(LoReg) in selectG_CONSTANT()
2295 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg) in selectG_FNEG()
2308 .addReg(LoReg) in selectG_FNEG()
2349 .addReg(LoReg) in selectG_FABS()
2609 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg) in selectG_PTRMASK()
2618 MaskedLo = LoReg; in selectG_PTRMASK()
[all …]
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| H A D | SILoadStoreOptimizer.cpp | 179 Register LoReg; member
1831 assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 || in computeBase()
1853 .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg) in computeBase()
1964 Addr.Base.LoReg = BaseLo.getReg(); in processBaseWithConstOffset()
2013 << MAddr.Base.LoReg << "} Offset: " << MAddr.Offset << "\n\n";); in promoteConstantOffsetToImm()
2069 if (MAddrNext.Base.LoReg != MAddr.Base.LoReg || in promoteConstantOffsetToImm()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5132 unsigned LoReg, ROpc, MOpc; in Select() local
5136 LoReg = X86::AL; in Select()
5141 LoReg = X86::AX; in Select()
5146 LoReg = X86::EAX; in Select()
5151 LoReg = X86::RAX; in Select()
5211 unsigned LoReg, HiReg; in Select() local
5224 LoReg = UseMULX ? X86::EDX : X86::EAX; in Select()
5234 LoReg = UseMULX ? X86::RDX : X86::RAX; in Select()
5350 unsigned LoReg, HiReg, ClrReg; in Select() local
5355 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 308 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
857 .addReg(LoReg); in expandBuildPairF64()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1974 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
1975 if (JumpReg == LoReg) in CMSEPushCalleeSaves()
1977 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
1994 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves() local
1995 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
2000 .addReg(LoReg, RegState::Kill); in CMSEPushCalleeSaves()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 9801 Register LoReg = MI.getOperand(0).getReg(); in emitReadCycleWidePseudo() local
9809 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg) in emitReadCycleWidePseudo()
9837 Register LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
9850 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) in emitSplitF64Pseudo()
9872 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
9883 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())) in emitBuildPairF64Pseudo()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12358 Register LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
12362 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()
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