| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; }
64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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| H A D | LanaiInstrInfo.cpp | 754 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
758 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth()
760 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth()
761 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth()
764 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth()
785 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
786 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
795 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
798 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth()
812 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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| H A D | LanaiInstrInfo.h | 71 const MachineInstr &LdSt,
76 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 301 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
304 unsigned Opc = LdSt.getOpcode(); in getMemOperandsWithOffsetWidth()
309 if (isDS(LdSt)) { in getMemOperandsWithOffsetWidth()
344 if (LdSt.mayLoad()) in getMemOperandsWithOffsetWidth()
347 assert(LdSt.mayStore()); in getMemOperandsWithOffsetWidth()
371 if (isMUBUF(LdSt) || isMTBUF(LdSt)) { in getMemOperandsWithOffsetWidth()
396 Width = getOpSize(LdSt, DataOpIdx); in getMemOperandsWithOffsetWidth()
400 if (isMIMG(LdSt)) { in getMemOperandsWithOffsetWidth()
414 Width = getOpSize(LdSt, DataOpIdx); in getMemOperandsWithOffsetWidth()
418 if (isSMRD(LdSt)) { in getMemOperandsWithOffsetWidth()
[all …]
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| H A D | SIInstrInfo.h | 196 const MachineInstr &LdSt,
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1163 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
1165 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffsetWidth()
1171 if (LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
1173 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
1176 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth()
1179 Width = (*LdSt.memoperands_begin())->getSize(); in getMemOperandWithOffsetWidth()
1180 BaseReg = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
1181 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
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| H A D | RISCVInstrInfo.h | 121 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2779 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3) in isLdStSafeToCluster()
2782 if (LdSt.getOperand(2).isFI()) in isLdStSafeToCluster()
2788 if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI)) in isLdStSafeToCluster()
5520 if (!LdSt.mayLoadOrStore() || LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
5524 if (!LdSt.getOperand(1).isImm() || in getMemOperandWithOffsetWidth()
5525 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI())) in getMemOperandWithOffsetWidth()
5527 if (!LdSt.getOperand(1).isImm() || in getMemOperandWithOffsetWidth()
5528 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI())) in getMemOperandWithOffsetWidth()
5531 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth()
5535 Offset = LdSt.getOperand(1).getImm(); in getMemOperandWithOffsetWidth()
[all …]
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| H A D | PPCInstrInfo.h | 632 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
640 const MachineInstr &LdSt,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2548 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
2584 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth()
2586 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) || in getMemOperandWithOffsetWidth()
2587 !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
2591 if (!LdSt.getOperand(1).isReg() || in getMemOperandWithOffsetWidth()
2592 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) || in getMemOperandWithOffsetWidth()
2593 !LdSt.getOperand(3).isImm()) in getMemOperandWithOffsetWidth()
2610 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth()
2611 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
2615 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
[all …]
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| H A D | AArch64InstrInfo.h | 157 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
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| H A D | AArch64SchedTSV110.td | 132 // MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
135 // 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2765 GLoadStore &LdSt = cast<GLoadStore>(I); in select() local
2775 uint64_t MemSizeInBytes = LdSt.getMemSize(); in select()
2783 assert(!isa<GZExtLoad>(LdSt)); in select()
2787 if (isa<GLoad>(LdSt)) { in select()
2800 Register ValReg = LdSt.getReg(0); in select()
2824 const Register ValReg = LdSt.getReg(0); in select()
2832 LLT MemTy = LdSt.getMMO().getMemoryType(); in select()
2842 LdSt.getOperand(0).setReg(Copy); in select()
2852 Register OldDst = LdSt.getReg(0); in select()
2855 LdSt.getOperand(0).setReg(NewDst); in select()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 208 const MachineInstr &LdSt,
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| H A D | HexagonInstrInfo.cpp | 3034 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
3038 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width); in getMemOperandsWithOffsetWidth()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 342 const MachineInstr &LdSt,
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleR52.td | 551 foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
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| H A D | ARMISelDAGToDAG.cpp | 1078 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
1079 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1084 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits()) in SelectAddrMode6Offset()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1365 if (auto *LdSt = dyn_cast<GLoadStore>(&UseMI)) { in matchPtrAddImmedChain() local
1366 AccessTy = getTypeForLLT(MRI.getType(LdSt->getReg(0)), in matchPtrAddImmedChain()
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