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Searched refs:LMUL (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/clang/lib/Support/
H A DRISCVVIntrinsicUtils.cpp78 : BT(BT), LMUL(LMULType(Log2LMUL)) { in RVVType()
328 ShortStr += LMUL.str(); in initShortStr()
621 LMUL.MulLog2LMUL(1); in applyModifier()
626 LMUL.MulLog2LMUL(2); in applyModifier()
631 LMUL.MulLog2LMUL(3); in applyModifier()
737 LMUL = LMULType(0); in applyModifier()
753 Scale = LMUL.getScale(ElementBitwidth); in applyLog2EEW()
764 Scale = LMUL.getScale(ElementBitwidth); in applyFixedSEW()
770 if (Log2LMUL < LMUL.Log2LMUL) { in applyFixedLog2LMUL()
776 if (Log2LMUL > LMUL.Log2LMUL) { in applyFixedLog2LMUL()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h143 uint16_t LMUL : 3; member
153 uint16_t LMUL : 3; member
163 uint16_t LMUL : 3; member
172 uint16_t LMUL : 3; member
183 uint16_t LMUL : 3; member
191 uint16_t LMUL : 3; member
200 uint16_t LMUL : 3; member
H A DRISCVExpandPseudoInsts.cpp297 unsigned LMUL = ZvlssegInfo->second; in expandVSPILL() local
298 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations."); in expandVSPILL()
303 if (LMUL == 2) { in expandVSPILL()
308 } else if (LMUL == 4) { in expandVSPILL()
314 assert(LMUL == 1 && "LMUL must be 1, 2, or 4."); in expandVSPILL()
347 unsigned LMUL = ZvlssegInfo->second; in expandVRELOAD() local
348 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations."); in expandVRELOAD()
353 if (LMUL == 2) { in expandVRELOAD()
358 } else if (LMUL == 4) { in expandVRELOAD()
364 assert(LMUL == 1 && "LMUL must be 1, 2, or 4."); in expandVRELOAD()
H A DRISCVISelDAGToDAG.cpp209 switch (LMUL) { in createTuple()
302 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG() local
311 SDValue Merge = createTuple(*CurDAG, Regs, NF, LMUL); in selectVLSEG()
321 static_cast<unsigned>(LMUL)); in selectVLSEG()
345 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEGFF() local
390 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLXSEG() local
448 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSSEG() local
450 SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); in selectVSSEG()
478 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSXSEG() local
480 SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); in selectVSXSEG()
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H A DRISCVRegisterInfo.td333 // There is no need to define register classes for fractional LMUL.
341 // The set of legal NF for LMUL = lmul.
342 // LMUL == 1, NF = 2, 3, 4, 5, 6, 7, 8
343 // LMUL == 2, NF = 2, 3, 4
344 // LMUL == 4, NF = 2
363 // Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX.
365 // For example, when LMUL = 4, the potential valid indexes is
367 // NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0.
371 // Use START = 0, LMUL = 4 and NF = 2 as the example,
374 // Use START = 1, LMUL = 4 and NF = 2 as the example,
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H A DRISCVInsertVSETVLI.cpp301 bool LMUL = false; member
308 return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy; in usedVTYPE()
314 LMUL = true; in demandVTYPE()
331 if (Used.LMUL && in areCompatibleVTYPEs()
383 Res.LMUL = false; in getDemanded()
398 Res.LMUL = false; in getDemanded()
1366 A.LMUL |= B.LMUL; in doUnion()
H A DRISCVTargetTransformInfo.cpp148 unsigned LMUL = PowerOf2Floor( in getRegisterBitWidth() local
155 ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0); in getRegisterBitWidth()
158 ST->hasVInstructions() ? LMUL * RISCV::RVVBitsPerBlock : 0); in getRegisterBitWidth()
H A DRISCVInstrInfoVPseudos.td73 // This class describes information associated to the LMUL.
86 // Associate LMUL with tablegen records of register classes.
307 // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
471 bits<3> LMUL = L;
487 bits<3> LMUL = L;
495 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
504 bits<3> LMUL = L;
537 bits<3> LMUL = L;
555 bits<3> LMUL = L;
573 bits<3> LMUL = L;
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H A DRISCVInstrInfo.cpp1453 #define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL) \ argument
1454 RISCV::PseudoV##OP##_##TYPE##_##LMUL
1594 #define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL) \ argument
1595 case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \
1596 Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
1727 #define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL) \ argument
1728 RISCV::PseudoV##OP##_##LMUL##_TIED
1742 #define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL) \ argument
1743 case RISCV::PseudoV##OP##_##LMUL##_TIED: \
1744 NewOpc = RISCV::PseudoV##OP##_##LMUL; \
H A DRISCVISelLowering.cpp1491 RISCVII::VLMUL LMUL = getLMUL(VT); in getSubregIndexByMVT() local
1492 if (LMUL == RISCVII::VLMUL::LMUL_F8 || in getSubregIndexByMVT()
1493 LMUL == RISCVII::VLMUL::LMUL_F4 || in getSubregIndexByMVT()
1494 LMUL == RISCVII::VLMUL::LMUL_F2 || in getSubregIndexByMVT()
1495 LMUL == RISCVII::VLMUL::LMUL_1) { in getSubregIndexByMVT()
1500 if (LMUL == RISCVII::VLMUL::LMUL_2) { in getSubregIndexByMVT()
1505 if (LMUL == RISCVII::VLMUL::LMUL_4) { in getSubregIndexByMVT()
4754 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT); in lowerVectorIntrinsicScalars() local
4760 LMUL); in lowerVectorIntrinsicScalars()
4769 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT); in lowerVectorIntrinsicScalars() local
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H A DRISCVInstrInfoV.td999 // group cannot overlap the mask register if used, unless LMUL=1.
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h392 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { in isValidLMUL() argument
393 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1); in isValidLMUL()
407 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) { in encodeLMUL() argument
408 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL"); in encodeLMUL()
409 unsigned LmulLog2 = Log2_32(LMUL); in encodeLMUL()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Driscv_vector.td26 // use the Log2LMUL [0, 1, 2, 3, -1, -2, -3] to represent the LMUL.
35 // be performed under LMUL=1 because mask registers are not grouped.
50 // definition of that particular builtin (for the given LMUL).
87 // no-op if the vector was already LMUL=1
99 // and LMUL), and computes another vector type which only changed LMUL as
103 // and LMUL), and computes another vector type which only changed LMUL as
129 // under LMUL=1).
1511 // and LMUL.
2136 // Reinterpret between different SEW under the same LMUL
2155 // LMUL truncation
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H A DDiagnosticSemaKinds.td11628 "LMUL argument must be in the range [0,3] or [5,7]">;
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-elen.ll8 ; This should use LMUL=1.
69 ; This should use LMUL=1 becuase there are no fractional i32 LMULs with ELEN=32
116 ; This should use LMUL=1.
153 ; This should use LMUL=1 becuase there are no fractional float LMULs with ELEN=32
H A Dvrgatherei16-subreg-liveness.ll6 ; register-allocated. The LMUL=1 destination register groups may not overlap
H A Dzve32-types.ll10 ; widened by using the next larger LMUL and operating on the whole vector. This
H A Dvsetvli-insert-crossbb.ll498 ; VTYPEs. The AVL is the same and the SEW/LMUL ratio implies the same VLMAX so
535 ; see two different vtypes with the same SEW/LMUL ratio. At if2.end we will only
536 ; know the SEW/LMUL ratio for the if.end predecessor and the full vtype for
537 ; the if2 predecessor. This makes sure we can merge a SEW/LMUL predecessor with
H A Dfixed-vectors-int-splat.ll682 ; This test used to crash at LMUL=8 when inserting a v16i64 subvector into
683 ; nxv8i64 at index 0: the v16i64 type was used to get the LMUL, the size of
/llvm-project-15.0.7/clang/include/clang/Support/
H A DRISCVVIntrinsicUtils.h175 LMULType LMUL; variable
193 RVVType() : BT(BasicType::Unknown), LMUL(0), Valid(false) {} in RVVType()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h59 LMUL, enumerator
H A DXCoreISelDAGToDAG.cpp190 case XCoreISD::LMUL: { in Select()
H A DXCoreISelLowering.cpp59 case XCoreISD::LMUL : return "XCoreISD::LMUL"; in getTargetNodeName()
562 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, in LowerUMUL_LOHI()
1704 case XCoreISD::LMUL: { in PerformDAGCombine()
1716 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), in PerformDAGCombine()
1744 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, in PerformDAGCombine()
1769 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, in PerformDAGCombine()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGDebugInfo.cpp758 unsigned LMUL; in CreateType() local
762 LMUL = 1; in CreateType()
766 LMUL = 64 / FixedSize; in CreateType()
768 LMUL = FixedSize / 64; in CreateType()
781 llvm::dwarf::DW_OP_div, llvm::dwarf::DW_OP_constu, LMUL}); in CreateType()