| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1182 if (!LHSReg) in emitAddSub()
1186 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1285 if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP || in emitAddSub_rr()
1309 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1368 assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP && in emitAddSub_rs()
1395 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1410 assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR && in emitAddSub_rx()
1439 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1493 if (!LHSReg) in emitFCmp()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
502 unsigned LHSReg, unsigned RHSReg, in validOpRegPair() argument
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
506 validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) && in validOpRegPair()
543 auto LHSReg = MIB.getReg(2); in selectCmp() local
545 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize, in selectCmp()
555 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg, in selectCmp()
561 if (!insertComparison(Helper, I, IntermediateRes, ARMConds.first, LHSReg, in selectCmp()
564 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg, in selectCmp()
576 unsigned LHSReg, unsigned RHSReg, in insertComparison() argument
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2137 Register LHSReg = getRegForValue(LHS); in X86FastEmitCMoveSelect() local
2138 if (!LHSReg || !RHSReg) in X86FastEmitCMoveSelect()
2191 Register LHSReg = getRegForValue(LHS); in X86FastEmitSSESelect() local
2336 Register LHSReg = getRegForValue(LHS); in X86FastEmitPseudoSelect() local
2338 if (!LHSReg || !RHSReg) in X86FastEmitPseudoSelect()
2344 fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); in X86FastEmitPseudoSelect()
2893 Register LHSReg = getRegForValue(LHS); in fastLowerIntrinsicCall() local
2894 if (LHSReg == 0) in fastLowerIntrinsicCall()
2912 .addReg(LHSReg); in fastLowerIntrinsicCall()
2935 .addReg(LHSReg); in fastLowerIntrinsicCall()
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2644 Register LHSReg = MI.getOperand(1).getReg(); in matchHoistLogicOpWithSameOpcodeHands() local
5424 Register LHSReg = MI.getOperand(1).getReg(); in matchCombineFSubFNegFMulToFMadOrFMA() local
5433 if (mi_match(LHSReg, MRI, m_GFNeg(m_MInstr(FMulMI))) && in matchCombineFSubFNegFMulToFMadOrFMA()
5434 (Aggressive || (MRI.hasOneNonDBGUse(LHSReg) && in matchCombineFSubFNegFMulToFMadOrFMA()
5455 FMulMI->getOperand(2).getReg(), LHSReg}); in matchCombineFSubFNegFMulToFMadOrFMA()
5471 Register LHSReg = MI.getOperand(1).getReg(); in matchCombineFSubFpExtFMulToFMadOrFMA() local
5480 if (mi_match(LHSReg, MRI, m_GFPExt(m_MInstr(FMulMI))) && in matchCombineFSubFpExtFMulToFMadOrFMA()
5482 (Aggressive || MRI.hasOneNonDBGUse(LHSReg))) { in matchCombineFSubFpExtFMulToFMadOrFMA()
5506 {NegY, FpExtZ, LHSReg}); in matchCombineFSubFpExtFMulToFMadOrFMA()
5524 Register LHSReg = MI.getOperand(1).getReg(); in matchCombineFSubFpExtFNegFMulToFMadOrFMA() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 312 Register LHSReg = getRegForValue(LHS); in emitLogicalOp() local
313 if (!LHSReg) in emitLogicalOp()
328 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
|