Lines Matching refs:LHSReg
205 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
208 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
211 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
215 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
224 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
241 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
243 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
248 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
250 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
252 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
1181 Register LHSReg = getRegForValue(LHS); in emitAddSub() local
1182 if (!LHSReg) in emitAddSub()
1186 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1192 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags, in emitAddSub()
1195 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags, in emitAddSub()
1199 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult); in emitAddSub()
1213 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, in emitAddSub()
1219 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0, in emitAddSub()
1238 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL, in emitAddSub()
1261 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType, in emitAddSub()
1277 return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult); in emitAddSub()
1280 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rr() argument
1283 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rr()
1285 if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP || in emitAddSub_rr()
1309 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1312 .addReg(LHSReg) in emitAddSub_rr()
1317 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_ri() argument
1320 assert(LHSReg && "Invalid register number."); in emitAddSub_ri()
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1356 .addReg(LHSReg) in emitAddSub_ri()
1362 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rs() argument
1367 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rs()
1368 assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP && in emitAddSub_rs()
1395 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1398 .addReg(LHSReg) in emitAddSub_rs()
1404 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rx() argument
1409 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rx()
1410 assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR && in emitAddSub_rx()
1439 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1442 .addReg(LHSReg) in emitAddSub_rx()
1476 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm) { in emitICmp_ri() argument
1477 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, Imm, in emitICmp_ri()
1492 Register LHSReg = getRegForValue(LHS); in emitFCmp() local
1493 if (!LHSReg) in emitFCmp()
1499 .addReg(LHSReg); in emitFCmp()
1509 .addReg(LHSReg) in emitFCmp()
1549 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg, in emitSubs_rr() argument
1551 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, in emitSubs_rr()
1555 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg, in emitSubs_rs() argument
1559 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType, in emitSubs_rs()
1580 Register LHSReg = getRegForValue(LHS); in emitLogicalOp() local
1581 if (!LHSReg) in emitLogicalOp()
1587 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm); in emitLogicalOp()
1608 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
1622 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
1633 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg); in emitLogicalOp()
1642 unsigned LHSReg, uint64_t Imm) { in emitLogicalOp_ri() argument
1677 fastEmitInst_ri(Opc, RC, LHSReg, in emitLogicalOp_ri()
1687 unsigned LHSReg, unsigned RHSReg, in emitLogicalOp_rs() argument
1719 fastEmitInst_rri(Opc, RC, LHSReg, RHSReg, in emitLogicalOp_rs()
1728 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, in emitAnd_ri() argument
1730 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, Imm); in emitAnd_ri()
3681 Register LHSReg = getRegForValue(LHS); in fastLowerIntrinsicCall() local
3682 if (!LHSReg) in fastLowerIntrinsicCall()
3690 MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3702 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3703 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3711 Register LHSReg = getRegForValue(LHS); in fastLowerIntrinsicCall() local
3712 if (!LHSReg) in fastLowerIntrinsicCall()
3720 MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3731 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3732 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg); in fastLowerIntrinsicCall()