Lines Matching refs:LHSReg
2137 Register LHSReg = getRegForValue(LHS); in X86FastEmitCMoveSelect() local
2138 if (!LHSReg || !RHSReg) in X86FastEmitCMoveSelect()
2143 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); in X86FastEmitCMoveSelect()
2191 Register LHSReg = getRegForValue(LHS); in X86FastEmitSSESelect() local
2195 if (!LHSReg || !RHSReg || !CmpLHSReg || !CmpRHSReg) in X86FastEmitSSESelect()
2222 ImplicitDefReg, LHSReg); in X86FastEmitSSESelect()
2243 Register VBlendReg = fastEmitInst_rrr(BlendOpcode, VR128, RHSReg, LHSReg, in X86FastEmitSSESelect()
2264 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg); in X86FastEmitSSESelect()
2336 Register LHSReg = getRegForValue(LHS); in X86FastEmitPseudoSelect() local
2338 if (!LHSReg || !RHSReg) in X86FastEmitPseudoSelect()
2344 fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); in X86FastEmitPseudoSelect()
2893 Register LHSReg = getRegForValue(LHS); in fastLowerIntrinsicCall() local
2894 if (LHSReg == 0) in fastLowerIntrinsicCall()
2912 .addReg(LHSReg); in fastLowerIntrinsicCall()
2914 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, CI->getZExtValue()); in fastLowerIntrinsicCall()
2922 ResultReg = fastEmit_rr(VT, VT, BaseOpc, LHSReg, RHSReg); in fastLowerIntrinsicCall()
2935 .addReg(LHSReg); in fastLowerIntrinsicCall()
2946 .addReg(LHSReg); in fastLowerIntrinsicCall()
2950 TLI.getRegClassFor(VT), LHSReg, RHSReg); in fastLowerIntrinsicCall()