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/llvm-project-15.0.7/bolt/test/X86/Inputs/
H A Djump-table-pic.s25 .L12: label
35 jmp .L12
38 jmp .L12
41 jmp .L12
H A Dexc_args.s143 jmp .L12
154 .L12: label
H A Dexc4sw.S119 je .L12
122 .L12: label
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Duserstack.ll55 ; CHECK-NEXT: i[[PTR]].sub $push[[L12:.+]]=, $pop[[L4]], $pop[[L5]]
56 ; CHECK-NEXT: local.tee $push[[L11:.+]]=, 0, $pop[[L12]]
82 ; CHECK-NEXT: i[[PTR]].sub $push[[L12:.+]]=, {{.+}}, $pop[[L2]]
83 ; CHECK-NEXT: local.tee $push[[L11:.+]]=, [[SP:.+]], $pop[[L12]]
170 ; CHECK-NEXT: i[[PTR]].const $push[[L12:.+]]=, 16
247 ; CHECK: local.get $push[[L12:.+]]=, [[STACK]]
248 ; CHECK-NEXT: global.set __stack_pointer, $pop[[L12]]
266 ; CHECK: local.get $push[[L12:.+]]=, [[FP]]
267 ; CHECK-NEXT: global.set __stack_pointer, $pop[[L12]]
286 ; CHECK: local.get $push[[L12:.+]]=, [[COPY]]
[all …]
H A Dstack-alignment.ll50 ; CHECK: i[[PTR]].sub $push[[L12:.+]]=, $pop[[L13]], $pop{{.+}}
51 ; CHECK: i[[PTR]].and $push[[L11:.+]]=, $pop[[L12]], $pop{{.+}}
H A Dreg-stackify.ll109 ; CHECK-NEXT: i32.const $push[[L12:[0-9]+]]=, 1{{$}}
110 ; CHECK-NEXT: i32.lt_s $push[[L3:[0-9]+]]=, $2, $pop[[L12]]{{$}}
262 ; CHECK-NEXT: i32.div_s $push[[L12:[0-9]+]]=, $pop[[L10]], $pop[[L11]]{{$}}
263 ; CHECK-NEXT: i32.div_s $push[[L13:[0-9]+]]=, $pop[[L9]], $pop[[L12]]{{$}}
/llvm-project-15.0.7/clang/test/Analysis/
H A Dcfg-indirect-goto-determinism.cpp16 (void)&&L12; in indirectBlockSuccessorDeterminism()
58 L12: in indirectBlockSuccessorDeterminism()
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/
H A Dopaque_ptr.ll14 ; CHECK-NEXT: [[L12:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
15 ; CHECK-NEXT: [[ADD:%.*]] = add i64 [[L01]], [[L12]]
/llvm-project-15.0.7/clang/test/Sema/
H A Dscope-check.c118 goto L12; in test8()
121 L12: in test8()
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/
H A Dint_sideeffect.ll15 ; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
21 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L12]], i32 1
53 ; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
59 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L12]], i32 1
/llvm-project-15.0.7/lldb/test/Shell/Expr/Inputs/
H A Dir-memory-map-basic15 L12 = malloc 128 128
H A Dir-memory-map-mix-malloc-free21 L12 = malloc 5 16
29 free L12
/llvm-project-15.0.7/clang/test/Parser/
H A Dcxx2a-template-lambdas.cpp22 auto L12 = []<auto> requires true noexcept {};
H A Dcxx2b-lambdas.cpp20 auto L12 = [] consteval {};
/llvm-project-15.0.7/lld/test/MachO/
H A Dloh-adrp-ldr-got-ldr.s59 L12: ldr x2, [x0] label
73 .loh AdrpLdrGotLdr L10, L11, L12
128 L12: ldr s1, [x1] label
H A Dloh-adrp-ldr.s51 L12: ldr x6, 0 label
138 .loh AdrpLdr L11, L12
/llvm-project-15.0.7/llvm/test/MC/MachO/
H A Dx86_64-symbols.s40 L12: label
H A Dx86_32-symbols.s40 L12: label
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/vect/
H A Dsetcc-v32.ll137 ; CHECK: [[L12:r[0-9:]+]] = vsxthw(r0)
139 ; CHECK: [[P12:p[0-3]+]] = vcmpw.gt([[R12]],[[L12]])
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp256 Value *L11, *L12, *L21, *L22; in getMaskedTypeForICmpPair() local
258 if (decomposeBitTestICmp(L1, L2, PredL, L11, L12, L2)) { in getMaskedTypeForICmpPair()
262 if (!match(L1, m_And(m_Value(L11), m_Value(L12)))) { in getMaskedTypeForICmpPair()
266 L12 = Constant::getAllOnesValue(L1->getType()); in getMaskedTypeForICmpPair()
284 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
287 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
304 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
309 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
328 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
346 B = L12; in getMaskedTypeForICmpPair()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InterleavedAccess/AArch64/
H A Dbinopshuffles.ll80 ; CHECK-NEXT: [[L12:%.*]] = fadd fast <4 x float> [[L103]], [[L86]]
81 ; CHECK-NEXT: ret <4 x float> [[L12]]
H A Dbinopshuffles-inseltpoison.ll80 ; CHECK-NEXT: [[L12:%.*]] = fadd fast <4 x float> [[L103]], [[L86]]
81 ; CHECK-NEXT: ret <4 x float> [[L12]]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DREADME-Thumb.txt158 L12:
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A DsplitMove_undefReg_mverifier.ll36 %L12 = load i8, i8* %0
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfold-vector-shuffle-crash.ll43 %L12 = load <8 x float>, ptr %A

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