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Searched refs:JALR (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dreloc-jalr.ll3 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R2,TAILCALL-32R2
7 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-64,JALR-64R2,TAILCALL-64R2
11 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R6,TAILCALL-32R6
15 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-64,JALR-64R6,TAILCALL-64R6
19 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R2,TAILCALL-32R2
23 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-64,JALR-64R2,TAILCALL-64R2
34 ; RUN: -O0 < %s | FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R2,PIC-NOTAILCALL-R2
41 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R6,PIC-NOTAILCALL-R6
45 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-64,JALR-64R6,PIC-NOTAILCALL-R6
49 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R2,PIC-NOTAILCALL-R2
[all …]
H A Deh-return32.ll47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
H A Deh-return64.ll48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
H A Dcopy-fp64.ll17 …; CHECK: dead $ra = JALR killed $t9, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, impli…
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll32 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
43 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
53 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
63 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
73 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
83 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
93 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
104 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
119 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
135 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
[all …]
H A Dindirectbr.ll23 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
24 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
29 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
30 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
H A Dstore.ll54 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
188 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
322 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
480 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
638 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
772 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
H A Dload.ll55 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
218 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
382 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
545 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
709 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
883 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
1069 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
1245 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
1408 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
H A Dfptosi.ll108 ; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
299 ; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp59 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
89 case Mips::JALR: in isCall()
H A DMipsInstPrinter.cpp303 case Mips::JALR: in printAlias()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp136 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
139 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td601 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
909 def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>;
910 def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>;
911 def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>;
912 def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>;
913 def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>;
914 def : InstAlias<"ret", (JALR X0, X1, 0), 4>;
1332 PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
1372 PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
1376 PseudoInstExpansion<(JALR X0, X1, 0)>;
[all …]
H A DRISCVInstrInfoC.td879 def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
891 def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
H A DRISCVInstrFormats.td145 def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;
H A DRISCVRegisterInfo.td149 // Don't use X1 or X5 for JALR since that is a hint to pop the return address
/llvm-project-15.0.7/lld/ELF/Arch/
H A DRISCV.cpp51 JALR = 0x67, enumerator
216 write32le(buf + 28, itype(JALR, 0, X_T3, 0)); in writePltHeader()
228 write32le(buf + 8, itype(JALR, X_T1, X_T3, 0)); in writePlt()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dmachine-outliner-cfi.mir106 # OUTLINED-NEXT: $x0 = JALR $x5, 0
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dinsn.s39 .insn i JALR, 0, a0, 10(a1)
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips32r6InstrInfo.td1000 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>,
1129 def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6;
1130 def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO,
H A DMipsDelaySlotFiller.cpp588 case Mips::JALR: in getEquivalentCallShort()
H A DMipsInstrInfo.cpp882 case Mips::JALR: in verifyInstruction()
H A DMipsAsmPrinter.cpp126 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td2255 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM, ISA_MIPS1;
2256 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>, ISA_MIPS1;
2280 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
2300 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
2688 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
3162 // (JALR GPR32:$dst)>;
H A DMipsSEISelDAGToDAG.cpp194 case Mips::JALR: in processFunctionAfterISel()

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