Searched refs:IsRegCall (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 637 bool IsRegCall = false; in LowerCall() local
647 IsRegCall = true; in LowerCall()
660 IsRegCall = true; in LowerCall()
669 IsRegCall = true; in LowerCall()
695 return DAG.getNode(IsRegCall ? CSKYISD::TAILReg : CSKYISD::TAIL, DL, in LowerCall()
699 Chain = DAG.getNode(IsRegCall ? CSKYISD::CALLReg : CSKYISD::CALL, DL, NodeTys, in LowerCall()
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | TargetInfo.cpp | 1843 if ((IsRegCall || IsVectorCall) && in classifyArgumentType()
3050 if (!IsRegCall && Size > 512) in classify()
3764 classify(Ty, 0, Lo, Hi, isNamedArg, IsRegCall); in classifyArgumentType()
3970 unsigned FreeIntRegs = IsRegCall ? 11 : 6; in computeInfo()
3971 unsigned FreeSSERegs = IsRegCall ? 16 : 8; in computeInfo()
4016 if (IsRegCall && it->type->isStructureOrClassType()) in computeInfo()
4321 if ((IsVectorCall || IsRegCall) && in classify()
4323 if (IsRegCall) { in classify()
4415 bool IsRegCall = CC == llvm::CallingConv::X86_RegCall; in computeInfo() local
4429 } else if (IsRegCall) { in computeInfo()
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| /llvm-project-15.0.7/clang/lib/AST/ |
| H A D | ItaniumMangle.cpp | 1475 bool IsRegCall = FD && in mangleUnqualifiedName() local
1483 else if (IsRegCall) in mangleUnqualifiedName()
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