| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZk.td | 76 let Predicates = [HasStdExtZknd, IsRV64] in {
81 } // Predicates = [HasStdExtZknd, IsRV64]
94 let Predicates = [HasStdExtZkne, IsRV64] in {
97 } // Predicates = [HasStdExtZkne, IsRV64]
115 let Predicates = [HasStdExtZknh, IsRV64] in {
120 } // Predicates = [HasStdExtZknh, IsRV64]
146 let Predicates = [HasStdExtZknd, IsRV64] in {
150 } // Predicates = [HasStdExtZknd, IsRV64]
164 let Predicates = [HasStdExtZkne, IsRV64] in {
167 } // Predicates = [HasStdExtZkne, IsRV64]
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| H A D | RISCVInstrInfoM.td | 49 let Predicates = [HasStdExtMOrZmmul, IsRV64] in {
52 } // Predicates = [HasStdExtMOrZmmul, IsRV64]
54 let Predicates = [HasStdExtM, IsRV64] in {
63 } // Predicates = [HasStdExtM, IsRV64]
84 let Predicates = [HasStdExtMOrZmmul, IsRV64] in
87 let Predicates = [HasStdExtM, IsRV64] in {
107 } // Predicates = [HasStdExtM, IsRV64]
109 let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in {
116 } // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba]
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| H A D | RISCVInstrInfoZb.td | 362 } // Predicates = [HasStdExtZba, IsRV64]
447 } // Predicates = [HasStdExtZbp, IsRV64]
481 } // Predicates = [HasStdExtZbt, IsRV64]
499 } // Predicates = [HasStdExtZbb, IsRV64]
530 } // Predicates = [HasStdExtZbr, IsRV64]
571 } // Predicates = [HasStdExtZbe, IsRV64]
600 } // Predicates = [HasStdExtZbm, IsRV64]
660 } // Predicates = [HasStdExtZba, IsRV64]
764 } // Predicates = [HasStdExtZbp, IsRV64]
792 } // Predicates = [HasStdExtZbp, IsRV64]
[all …]
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| H A D | RISCVInstrInfoC.td | 324 let Predicates = [HasStdExtC, IsRV64] in
358 let Predicates = [HasStdExtC, IsRV64] in
399 Predicates = [HasStdExtC, IsRV64] in
509 let Predicates = [HasStdExtC, IsRV64] in
569 let Predicates = [HasStdExtC, IsRV64] in
759 } // Predicates = [HasStdExtC, IsRV64]
779 } // Predicates = [HasStdExtC, IsRV64]
796 } // Predicates = [HasStdExtC, IsRV64]
841 } // Predicates = [HasStdExtC, IsRV64]
876 } // Predicates = [HasStdExtC, IsRV64]
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| H A D | RISCVInstrInfoD.td | 56 def D64Ext : ExtInfo<0, [HasStdExtD, IsRV64]>;
57 def ZdinxExt : ExtInfo<1, [HasStdExtZdinx, IsRV64]>;
185 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
197 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
228 let Predicates = [HasStdExtZdinx, IsRV64] in {
236 } // Predicates = [HasStdExtZdinx, IsRV64]
260 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
389 let Predicates = [HasStdExtD, IsRV64] in {
429 } // Predicates = [HasStdExtD, IsRV64]
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| H A D | RISCVInstrInfoA.td | 80 let Predicates = [HasStdExtA, IsRV64] in {
102 } // Predicates = [HasStdExtA, IsRV64]
305 let Predicates = [HasStdExtA, IsRV64] in {
380 } // Predicates = [HasStdExtA, IsRV64]
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| H A D | RISCVInstrInfoZfh.td | 42 def Zfh64Ext : ExtInfo<0, [HasStdExtZfh, IsRV64]>;
46 def Zhinx64Ext : ExtInfo<1, [HasStdExtZhinx, IsRV64]>;
262 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
383 let Predicates = [HasStdExtZfh, IsRV64] in {
411 } // Predicates = [HasStdExtZfh, IsRV64]
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| H A D | RISCVInstrInfo.td | 722 let Predicates = [IsRV64] in {
747 } // Predicates = [IsRV64]
809 let Predicates = [IsRV64] in {
852 let Predicates = [IsRV64] in {
856 } // Predicates = [IsRV64]
863 let Predicates = [IsRV64] in {
866 } // Predicates = [IsRV64]
997 let Predicates = [IsRV64] in {
1013 } // Predicates = [IsRV64]
1640 } // Predicates = [IsRV64]
[all …]
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| H A D | RISCVFrameLowering.cpp | 64 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSPrologue() local
69 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue()
114 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSEpilogue() local
119 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue()
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| H A D | RISCVInstrInfoF.td | 106 def F64Ext : ExtInfo<0, [HasStdExtF, IsRV64]>;
108 def Zfinx64Ext : ExtInfo<1, [HasStdExtZfinx, IsRV64]>;
493 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
603 let Predicates = [HasStdExtF, IsRV64] in {
637 } // Predicates = [HasStdExtF, IsRV64]
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| H A D | RISCVInstrInfoV.td | 913 let Predicates = [IsRV64, HasVInstructionsI64] in {
916 } // [IsRV64, HasVInstructionsI64]
1582 let Predicates = [HasVInstructionsI64, IsRV64] in {
1598 } // Predicates = [HasVInstructionsI64, IsRV64]
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| H A D | RISCV.td | 439 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
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| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | TargetParser.h | 171 bool checkCPUKind(CPUKind Kind, bool IsRV64);
172 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
174 CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
176 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
177 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
179 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
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| /llvm-project-15.0.7/llvm/lib/Support/ |
| H A D | TargetParser.cpp | 272 bool checkCPUKind(CPUKind Kind, bool IsRV64) { in checkCPUKind() argument
275 return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64; in checkCPUKind()
278 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) { in checkTuneCPUKind() argument
281 return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64; in checkTuneCPUKind()
291 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64) { in resolveTuneCPUAlias() argument
298 CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) { in parseTuneCPUKind() argument
299 TuneCPU = resolveTuneCPUAlias(TuneCPU, IsRV64); in parseTuneCPUKind()
312 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidCPUArchList() argument
314 if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit()) in fillValidCPUArchList()
319 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidTuneCPUArchList() argument
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.cpp | 40 bool IsRV64 = TT.isArch64Bit(); in computeTargetABI() local
47 } else if (ABIName.startswith("ilp32") && IsRV64) { in computeTargetABI()
51 } else if (ABIName.startswith("lp64") && !IsRV64) { in computeTargetABI()
66 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
107 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
108 unsigned XLen = IsRV64 ? 64 : 32; in parseFeatureBits()
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| H A D | RISCVMatInt.cpp | 51 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit]; in generateInstSeqImpl() local
68 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
74 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); in generateInstSeqImpl()
383 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit]; in getIntMatCost() local
385 int PlatRegSize = IsRV64 ? 64 : 32; in getIntMatCost()
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| H A D | RISCVBaseInfo.h | 381 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 281 bool IsRV64; member
319 IsRV64 = o.IsRV64; in RISCVOperand()
780 bool isRV64() const { return IsRV64; } in isRV64()
837 bool IsRV64) { in createToken()
842 Op->IsRV64 = IsRV64; in createToken()
847 SMLoc E, bool IsRV64, in createReg()
853 Op->IsRV64 = IsRV64; in createReg()
864 Op->IsRV64 = IsRV64; in createImm()
876 Op->IsRV64 = IsRV64; in createSysReg()
881 bool IsRV64) { in createVType()
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| /llvm-project-15.0.7/clang/lib/Driver/ToolChains/ |
| H A D | RISCVToolchain.cpp | 159 bool IsRV64 = ToolChain.getArch() == llvm::Triple::riscv64; in ConstructJob() local
161 if (IsRV64) { in ConstructJob()
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| H A D | Gnu.cpp | 1748 bool IsRV64 = TargetTriple.getArch() == llvm::Triple::riscv64; in findRISCVMultilibs() local
1751 addMultilibFlag(!IsRV64, "m32", Flags); in findRISCVMultilibs()
1752 addMultilibFlag(IsRV64, "m64", Flags); in findRISCVMultilibs()
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