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Searched refs:IsROTL (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2034 bool IsROTL = (Op.getOpcode() == ISD::ROTL); in SimplifyDemandedBits() local
2046 APInt Demanded0 = DemandedBits.rotr(IsROTL ? Amt : RevAmt); in SimplifyDemandedBits()
2057 DemandedBits.countTrailingZeros() >= (IsROTL ? Amt : RevAmt)) { in SimplifyDemandedBits()
2058 Op1 = TLO.DAG.getConstant(IsROTL ? Amt : RevAmt, dl, Op1.getValueType()); in SimplifyDemandedBits()
2062 DemandedBits.countLeadingZeros() >= (IsROTL ? RevAmt : Amt)) { in SimplifyDemandedBits()
2063 Op1 = TLO.DAG.getConstant(IsROTL ? RevAmt : Amt, dl, Op1.getValueType()); in SimplifyDemandedBits()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp30565 bool IsROTL = Opcode == ISD::ROTL; in LowerRotate() local
30597 if (!IsROTL) { in LowerRotate()
30617 assert(IsROTL && "Only ROTL expected"); in LowerRotate()
30680 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
30697 if (IsROTL) in LowerRotate()
30737 if (!IsROTL && !useVPTERNLOG(Subtarget, VT)) { in LowerRotate()
30739 IsROTL = true; in LowerRotate()
30742 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
30798 if (!IsROTL) { in LowerRotate()
30800 IsROTL = true; in LowerRotate()
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