Lines Matching refs:IsROTL
30565 bool IsROTL = Opcode == ISD::ROTL; in LowerRotate() local
30579 unsigned RotOpc = IsROTL ? X86ISD::VROTLI : X86ISD::VROTRI; in LowerRotate()
30591 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
30597 if (!IsROTL) { in LowerRotate()
30617 assert(IsROTL && "Only ROTL expected"); in LowerRotate()
30659 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
30662 unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI; in LowerRotate()
30669 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL); in LowerRotate()
30680 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
30697 if (IsROTL) in LowerRotate()
30713 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL); in LowerRotate()
30737 if (!IsROTL && !useVPTERNLOG(Subtarget, VT)) { in LowerRotate()
30739 IsROTL = true; in LowerRotate()
30742 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
30743 unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL; in LowerRotate()
30792 SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt); in LowerRotate()
30793 SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR); in LowerRotate()
30798 if (!IsROTL) { in LowerRotate()
30800 IsROTL = true; in LowerRotate()
30806 assert(IsROTL && "Only ROTL supported"); in LowerRotate()