| /llvm-project-15.0.7/llvm/unittests/Analysis/ |
| H A D | VectorFunctionABITest.cpp | 89 bool IsMasked() const { in IsMasked() function in __anon36cf3bb40111::VFABIParserTest
178 EXPECT_FALSE(IsMasked()); in TEST_F()
197 EXPECT_FALSE(IsMasked()); in TEST_F()
208 EXPECT_FALSE(IsMasked()); in TEST_F()
224 EXPECT_TRUE(IsMasked()); in TEST_F()
233 EXPECT_TRUE(IsMasked()); in TEST_F()
434 EXPECT_TRUE(IsMasked()); in TEST_F()
445 EXPECT_TRUE(IsMasked()); in TEST_F()
456 EXPECT_TRUE(IsMasked()); in TEST_F()
467 EXPECT_TRUE(IsMasked()); in TEST_F()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.h | 93 bool IsMasked, bool IsStridedOrIndexed,
97 void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
98 void selectVLSEGFF(SDNode *Node, bool IsMasked);
99 void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
100 void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
101 void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
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| H A D | RISCVISelDAGToDAG.cpp | 264 if (IsMasked) { in addVectorLoadStoreOperands()
280 if (IsMasked && IsLoad) { in addVectorLoadStoreOperands()
309 bool IsTU = IsMasked || !isAllUndef(Regs); in selectVLSEG()
352 bool IsTU = IsMasked || !isAllUndef(Regs); in selectVLSEGFF()
397 bool IsTU = IsMasked || !isAllUndef(Regs); in selectVLXSEG()
444 if (IsMasked) in selectVSSEG()
474 if (IsMasked) in selectVSXSEG()
1334 bool IsMasked = IntNo == Intrinsic::riscv_vle_mask || in Select() local
1373 bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask; in Select() local
1518 IsMasked, /*TU*/ false, IsOrdered, IndexLog2EEW, in Select()
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| H A D | RISCVExpandAtomicPseudoInsts.cpp | 52 bool IsMasked, int Width,
56 AtomicRMWInst::BinOp, bool IsMasked, int Width,
59 MachineBasicBlock::iterator MBBI, bool IsMasked,
343 AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width, in expandAtomicBinOp() argument
363 if (!IsMasked) in expandAtomicBinOp()
392 AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width, in expandAtomicMinMaxOp() argument
394 assert(IsMasked == true && in expandAtomicMinMaxOp()
512 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked, in expandAtomicCmpXchg() argument
541 static_cast<AtomicOrdering>(MI.getOperand(IsMasked ? 6 : 5).getImm()); in expandAtomicCmpXchg()
543 if (!IsMasked) { in expandAtomicCmpXchg()
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| H A D | RISCVISelLowering.cpp | 4720 bool IsMasked = NumOps == 7; in lowerVectorIntrinsicScalars() local
4787 if (IsMasked) in lowerVectorIntrinsicScalars()
4808 if (!IsMasked) in lowerVectorIntrinsicScalars()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | VFABIDemangling.cpp | 50 ParseRet tryParseMask(StringRef &MangledName, bool &IsMasked) { in tryParseMask() argument
52 IsMasked = true; in tryParseMask()
57 IsMasked = false; in tryParseMask()
336 bool IsMasked; in tryDemangleForVFABI() local
337 if (tryParseMask(MangledName, IsMasked) != ParseRet::OK) in tryDemangleForVFABI()
410 if (IsMasked) { in tryDemangleForVFABI()
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| /llvm-project-15.0.7/clang/lib/Support/ |
| H A D | RISCVVIntrinsicUtils.cpp | 850 StringRef OverloadedSuffix, StringRef IRName, bool IsMasked, in RVVIntrinsic() argument
855 : IRName(IRName), IsMasked(IsMasked), HasVL(HasVL), Scheme(Scheme), in RVVIntrinsic()
871 if (IsMasked) { in RVVIntrinsic()
883 if ((IsMasked && HasMaskedOffOperand) || in RVVIntrinsic()
884 (!IsMasked && hasPassthruOperand())) { in RVVIntrinsic()
914 bool IsMasked, bool HasMaskedOffOperand, in computeBuiltinTypes() argument
918 if (IsMasked) { in computeBuiltinTypes()
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| /llvm-project-15.0.7/clang/include/clang/Support/ |
| H A D | RISCVVIntrinsicUtils.h | 292 bool IsMasked; variable
308 llvm::StringRef IRName, bool IsMasked, bool HasMaskedOffOperand,
329 bool isMasked() const { return IsMasked; } in isMasked()
347 bool IsMasked, bool HasMaskedOffOperand, bool HasVL,
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4619 bool IsMasked = InMask.getNode() != nullptr; in tryVPTESTM() local
4639 if (IsMasked) { in tryVPTESTM()
4650 IsMasked); in tryVPTESTM()
4656 if (IsMasked) { in tryVPTESTM()
4671 if (IsMasked) in tryVPTESTM()
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| H A D | X86ISelLowering.cpp | 26247 bool IsMasked = false; in getTargetVShiftNode() local
26257 IsMasked = true; in getTargetVShiftNode()
26270 IsMasked = true; in getTargetVShiftNode()
26283 if (!IsMasked && AmtVT.getScalarSizeInBits() < 64) { in getTargetVShiftNode()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 16198 IsMasked = true; in getCombineLoadStoreParts()
16208 IsMasked = true; in getCombineLoadStoreParts()
16225 bool IsMasked = false; in CombineToPreIndexedLoadStore() local
16272 SDValue Val = IsMasked ? cast<MaskedStoreSDNode>(N)->getValue() in CombineToPreIndexedLoadStore()
16349 if (!IsMasked) { in CombineToPreIndexedLoadStore()
16463 bool IsMasked = false; in shouldCombineToPostInc() local
16466 IsMasked, OtherPtr, TLI)) { in shouldCombineToPostInc()
16486 bool &IsMasked, SDValue &Ptr, in getPostIndexedLoadStoreOp() argument
16492 IsMasked, Ptr, TLI) || in getPostIndexedLoadStoreOp()
16530 bool IsMasked = false; in CombineToPostIndexedLoadStore() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 19569 bool isSEXTLoad, bool IsMasked, bool isLE, in getMVEIndexedAddressParts() argument
19580 bool CanChangeType = isLE && !IsMasked; in getMVEIndexedAddressParts()
19636 bool IsMasked = false; in getPreIndexedAddressParts() local
19651 IsMasked = true; in getPreIndexedAddressParts()
19656 IsMasked = true; in getPreIndexedAddressParts()
19665 Ptr.getNode(), VT, Alignment, isSEXTLoad, IsMasked, in getPreIndexedAddressParts()
19694 bool IsMasked = false; in getPostIndexedAddressParts() local
19712 IsMasked = true; in getPostIndexedAddressParts()
19718 IsMasked = true; in getPostIndexedAddressParts()
19744 getMVEIndexedAddressParts(Op, VT, Alignment, isSEXTLoad, IsMasked, in getPostIndexedAddressParts()
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