| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | DFAPacketizer.h | 50 const InstrItineraryData *InstrItins;
57 DFAPacketizer(const InstrItineraryData *InstrItins, Automaton<uint64_t> a, in DFAPacketizer() argument
59 : InstrItins(InstrItins), A(std::move(a)), ItinActions(ItinActions) { in DFAPacketizer()
101 const InstrItineraryData *getInstrItins() const { return InstrItins; } in getInstrItins()
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| H A D | TargetSchedule.h | 34 InstrItineraryData InstrItins; variable
84 return &InstrItins; in getInstrItineraries()
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| H A D | ResourcePriorityQueue.h | 62 const InstrItineraryData* InstrItins; variable
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 43 return EnableSchedItins && !InstrItins.isEmpty(); in hasInstrItineraries()
66 STI->initInstrItins(InstrItins); in init()
109 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
110 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI); in getNumMicroOps()
193 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, in computeOperandLatency()
198 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx); in computeOperandLatency()
204 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); in computeOperandLatency()
278 return TII->getInstrLatency(&InstrItins, *MI); in computeInstrLatency()
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| H A D | PostRASchedulerList.cpp | 209 const InstrItineraryData *InstrItins = in SchedulePostRATDList() local
213 InstrItins, this); in SchedulePostRATDList()
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| H A D | MachinePipeliner.cpp | 986 const InstrItineraryData *InstrItins; member
991 : InstrItins(TSI.getInstrItineraryData()), STI(&TSI) {} in FuncUnitSorter()
1000 if (InstrItins && !InstrItins->isEmpty()) { in minFuncUnits()
1002 make_range(InstrItins->beginStage(SchedClass), in minFuncUnits()
1003 InstrItins->endStage(SchedClass))) { in minFuncUnits()
1046 if (InstrItins && !InstrItins->isEmpty()) { in calcCriticalResources()
1048 make_range(InstrItins->beginStage(SchedClass), in calcCriticalResources()
1049 InstrItins->endStage(SchedClass))) { in calcCriticalResources()
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| H A D | TwoAddressInstructionPass.cpp | 93 const InstrItineraryData *InstrItins; member in __anon568a009d0111::TwoAddressInstructionPass
849 if (TII->getInstrLatency(InstrItins, *MI) > 1) in rescheduleMIBelowKill()
983 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) in isDefTooClose()
1693 InstrItins = MF->getSubtarget().getInstrItineraryData(); in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600Subtarget.h | 43 InstrItineraryData InstrItins; variable
65 return &InstrItins; in getInstrItineraryData()
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| H A D | R600Subtarget.cpp | 31 InstrItins(getInstrItineraryForCPU(GPU)) {} in R600Subtarget()
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| H A D | GCNSubtarget.h | 62 InstrItineraryData InstrItins; variable
259 return &InstrItins; in getInstrItineraryData()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kSubtarget.h | 57 InstrItineraryData InstrItins; variable
164 return &InstrItins; in getInstrItineraryData()
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| H A D | M68kSubtarget.cpp | 98 InstrItins = getInstrItineraryForCPU(CPUName); in initializeSubtargetDependencies()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.h | 211 InstrItineraryData InstrItins; variable
396 return &InstrItins; in getInstrItineraryData()
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| H A D | MipsSubtarget.cpp | 250 InstrItins = getInstrItineraryForCPU(CPUName); in initializeSubtargetDependencies()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.h | 108 InstrItineraryData InstrItins; variable
122 return &InstrItins; in getInstrItineraryData()
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| H A D | HexagonSubtarget.cpp | 90 InstrItins(getInstrItineraryForCPU(CPUString)) { in HexagonSubtarget()
94 assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized"); in HexagonSubtarget()
498 int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0, in adjustSchedDependency()
597 int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI, in restoreLatency()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.h | 88 InstrItineraryData InstrItins; variable
211 return &InstrItins; in getInstrItineraryData()
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| H A D | PPCSubtarget.cpp | 172 InstrItins = getInstrItineraryForCPU(CPUName); in initSubtargetFeatures()
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| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 333 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { in initInstrItins()
334 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.h | 225 InstrItineraryData InstrItins; variable
492 return &InstrItins; in getInstrItineraryData()
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| H A D | ARMSubtarget.cpp | 201 InstrItins = getInstrItineraryForCPU(CPUString); in initSubtargetFeatures()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 50 : ScheduleDAG(mf), InstrItins(mf.getSubtarget().getInstrItineraryData()) {} in ScheduleDAGSDNodes()
627 if (!InstrItins || InstrItins->isEmpty()) { in computeLatency()
641 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
657 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
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| H A D | ScheduleDAGSDNodes.h | 50 const InstrItineraryData *InstrItins; variable
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| H A D | ResourcePriorityQueue.cpp | 44 : Picker(this), InstrItins(IS->MF->getSubtarget().getInstrItineraryData()) { in ResourcePriorityQueue()
312 if (Packet.size() >= InstrItins->SchedModel.IssueWidth) { in reserveResources()
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| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 217 void initInstrItins(InstrItineraryData &InstrItins) const;
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