| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | IVDescriptors.cpp | 631 RecurrenceDescriptor::InstDesc
645 return InstDesc(false, I); in isSelectCmpPattern()
655 return InstDesc(false, I); in isSelectCmpPattern()
661 return InstDesc(false, I); in isSelectCmpPattern()
667 RecurrenceDescriptor::InstDesc
673 return InstDesc(false, I); in isMinMaxPattern()
687 return InstDesc(false, I); in isMinMaxPattern()
711 return InstDesc(false, I); in isMinMaxPattern()
723 RecurrenceDescriptor::InstDesc
727 return InstDesc(false, I); in isConditionalRdxPattern()
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| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | IVDescriptors.h | 86 class InstDesc {
88 InstDesc(bool IsRecur, Instruction *I, Instruction *ExactFP = nullptr)
92 InstDesc(Instruction *I, RecurKind K, Instruction *ExactFP = nullptr)
124 static InstDesc isRecurrenceInstr(Loop *L, PHINode *Phi, Instruction *I,
125 RecurKind Kind, InstDesc &Prev,
141 static InstDesc isMinMaxPattern(Instruction *I, RecurKind Kind,
142 const InstDesc &Prev);
150 static InstDesc isSelectCmpPattern(Loop *Loop, PHINode *OrigPhi,
151 Instruction *I, InstDesc &Prev);
155 static InstDesc isConditionalRdxPattern(RecurKind Kind, Instruction *I);
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 160 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
218 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst() argument
223 auto InstID = std::make_pair(InstDesc->getOpcode(), Subtarget); in shouldReplaceInst()
228 unsigned SCIdx = InstDesc->getSchedClass(); in shouldReplaceInst()
256 if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost) in shouldReplaceInst()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 58 uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr,
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| H A D | ARMMCTargetDesc.cpp | 187 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget() argument
192 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8; in evaluateBranchTarget()
199 if (InstDesc.getOpcode() == ARM::tBLXi) in evaluateBranchTarget()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 435 const MCInstrDesc &InstDesc = MI->getDesc(); in tryAddToFoldList() local
436 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo]; in tryAddToFoldList()
444 for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) { in tryAddToFoldList()
1554 const MCInstrDesc &InstDesc = UseMI->getDesc(); in tryFoldRegSequence() local
1556 TII->getRegClass(InstDesc, OpIdx, TRI, *MI.getMF()); in tryFoldRegSequence()
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| H A D | SIInstrInfo.cpp | 3724 const MCInstrDesc &InstDesc = MI.getDesc(); in isImmOperandLegal() local
3725 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo]; in isImmOperandLegal()
3746 if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo)) in isImmOperandLegal()
4980 const MCInstrDesc &InstDesc = MI.getDesc(); in isOperandLegal() local
4981 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; in isOperandLegal()
5004 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) { in isOperandLegal()
5010 (AMDGPU::isSISrcOperand(InstDesc, i) && in isOperandLegal()
5011 isLiteralConstantLike(Op, InstDesc.OpInfo[i]))) { in isOperandLegal()
6718 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitUnaryOp() local
6848 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitBinaryOp() local
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 351 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode()); in isMacroFused() local
352 if (!InstDesc.isConditionalBranch()) in isMacroFused()
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| /llvm-project-15.0.7/bolt/lib/Target/X86/ |
| H A D | X86MCPlusBuilder.cpp | 2816 const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode()); in replaceRegWithImm() local
2819 for (unsigned Index = InstDesc.getNumDefs() + (I.HasLHS ? 1 : 0), in replaceRegWithImm()
2820 E = InstDesc.getNumOperands(); in replaceRegWithImm()
2883 const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode()); in replaceRegWithReg() local
2888 for (unsigned Index = InstDesc.getNumDefs() + (HasLHS ? 1 : 0), in replaceRegWithReg()
2889 E = InstDesc.getNumOperands(); in replaceRegWithReg()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2091 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); in addLiteralImmOperand() local
2094 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2097 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2098 const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum); in addLiteralImmOperand()
2103 uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType; in addLiteralImmOperand()
2120 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
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