3724   const MCInstrDesc &InstDesc = MI.getDesc();  in isImmOperandLegal()  local
3725   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];  in isImmOperandLegal()
3746   if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))  in isImmOperandLegal()
4980   const MCInstrDesc &InstDesc = MI.getDesc();  in isOperandLegal()  local
4981   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];  in isOperandLegal()
5004             usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {  in isOperandLegal()
5009       } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32 ||  in isOperandLegal()
5010                  (AMDGPU::isSISrcOperand(InstDesc, i) &&  in isOperandLegal()
5011                   isLiteralConstantLike(Op, InstDesc.OpInfo[i]))) {  in isOperandLegal()
6718   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitUnaryOp()  local
6733   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);  in splitScalar64BitUnaryOp()
6739   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);  in splitScalar64BitUnaryOp()
6848   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitBinaryOp()  local
6874   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitBinaryOp()
6879   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitBinaryOp()
6952   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);  in splitScalar64BitBCNT()  local
6967   BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);  in splitScalar64BitBCNT()
6969   BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);  in splitScalar64BitBCNT()