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Searched refs:ImplicitUses (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h206 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr variable
565 const MCPhysReg *getImplicitUses() const { return ImplicitUses; } in getImplicitUses()
569 if (!ImplicitUses) in getNumImplicitUses()
572 for (; ImplicitUses[i]; ++i) /*empty*/ in getNumImplicitUses()
602 if (const MCPhysReg *ImpUses = ImplicitUses) in hasImplicitUseOfPhysReg()
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DResourceManager.cpp291 uint64_t ImplicitUses = Desc.ImplicitlyUsedProcResUnits; in checkAvailability() local
292 while (ImplicitUses) { in checkAvailability()
293 uint64_t Use = ImplicitUses & -ImplicitUses; in checkAvailability()
294 ImplicitUses ^= Use; in checkAvailability()
/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp355 const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses(); in getTouchedRegs() local
357 Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false); in getTouchedRegs()
389 const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses(); in getUsedRegs() local
391 Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true); in getUsedRegs()
422 const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses(); in getSrcRegs() local
424 Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true); in getSrcRegs()
445 if (const uint16_t *ImpUses = InstInfo.ImplicitUses) { in hasUseOfPhysReg()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DParallelSnippetGenerator.cpp193 BitVector ImplicitUses(State.getRegInfo().getNumRegs()); in generateCodeTemplates() local
199 ImplicitUses.set(Op.getImplicitReg()); in generateCodeTemplates()
207 getAliasedBits(State.getRegInfo(), ImplicitUses); in generateCodeTemplates()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DRegReAssign.cpp149 const MCPhysReg *ImplicitUses = Desc.getImplicitUses(); in rankRegisters() local
150 while (ImplicitUses && *ImplicitUses) { in rankRegisters()
152 BC.MIB->getAliases(*ImplicitUses, false).find_first(); in rankRegisters()
155 ++ImplicitUses; in rankRegisters()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DInstrDocsEmitter.cpp198 if (!II->ImplicitUses.empty()) { in EmitInstrDocs()
201 for (Record *Use : II->ImplicitUses) in EmitInstrDocs()
H A DCodeGenInstruction.h234 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
H A DCodeGenInstruction.cpp420 ImplicitUses = R->getValueAsListOfDefs("Uses"); in CodeGenInstruction()
H A DGlobalISelEmitter.cpp3137 if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) { in emitActionOpcodes()
3147 for (auto Use : I->ImplicitUses) { in emitActionOpcodes()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp166 if (const MCPhysReg *R = D.ImplicitUses) in getDefsUses()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineInstr.cpp92 if (MCID->ImplicitUses) in addImplicitDefUseOperands()
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp1366 if (MCID.ImplicitUses) in verifyImplicitOperands()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2742 if (NewDesc.ImplicitUses) in optimizeCompareInstr()
/llvm-project-15.0.7/llvm/docs/
H A DCodeGenerator.rst1360 ``TargetInstrInfo::get(opcode)::ImplicitUses``. Pre-colored registers impose
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3316 unsigned Reg = Desc.ImplicitUses[i]; in findImplicitSGPRReadInVOP()