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Searched refs:ImmVal (Results 1 – 25 of 38) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86EvexToVex.cpp179 int64_t ImmVal = Imm.getImm(); in performCustomAdjustments() local
181 Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1)); in performCustomAdjustments()
201 int64_t ImmVal = Imm.getImm(); in performCustomAdjustments() local
203 if ((ImmVal & 0xf) != ImmVal) in performCustomAdjustments()
H A DX86InstrInfo.h335 int64_t &ImmVal) const override;
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInst.h50 int64_t ImmVal; member
82 return ImmVal; in getImm()
87 ImmVal = Val; in setImm()
144 Op.ImmVal = Val; in createImm()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp581 int64_t ImmVal; in FoldImmediate() local
592 ImmVal = in FoldImmediate()
594 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n"); in FoldImmediate()
606 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n"); in FoldImmediate()
711 if (isInt<7>(ImmVal)) { in FoldImmediate()
715 } else if (isMImmVal(ImmVal)) { in FoldImmediate()
718 ImmVal = val2MImm(ImmVal); in FoldImmediate()
725 if (!isInt<7>(ImmVal)) in FoldImmediate()
732 if (!isMImmVal(ImmVal)) in FoldImmediate()
735 ImmVal = val2MImm(ImmVal); in FoldImmediate()
[all …]
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DPredicateExpander.cpp22 int ImmVal, in expandCheckImmOperand() argument
30 OS << (shouldNegate() ? " != " : " == ") << ImmVal; in expandCheckImmOperand()
34 StringRef ImmVal, in expandCheckImmOperand() argument
36 if (ImmVal.empty()) in expandCheckImmOperand()
45 OS << (shouldNegate() ? " != " : " == ") << ImmVal; in expandCheckImmOperand()
H A DPredicateExpander.h58 void expandCheckImmOperand(raw_ostream &OS, int OpIndex, int ImmVal,
60 void expandCheckImmOperand(raw_ostream &OS, int OpIndex, StringRef ImmVal,
H A DAsmMatcherEmitter.cpp449 int64_t ImmVal; member
479 X.ImmVal = Val; in getImmOp()
1904 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm(); in buildAliasResultOperands() local
1905 ResOperands.push_back(ResOperand::getImmOp(ImmVal)); in buildAliasResultOperands()
2184 int64_t Val = OpInfo.ImmVal; in emitConvertFuncs()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp353 return Kind == ER.Kind && V.ImmVal == ER.V.ImmVal; in operator ==()
513 OS << "imm:" << ER.V.ImmVal; in operator <<()
528 OS << "tgi:" << ER.V.ImmVal; in operator <<()
531 OS << "cpi:" << ER.V.ImmVal; in operator <<()
534 OS << "jti:" << ER.V.ImmVal; in operator <<()
537 OS << "???:" << ER.V.ImmVal; in operator <<()
699 V.ImmVal = 0; in ExtRoot()
711 V.ImmVal = Op.getIndex(); in ExtRoot()
727 return V.ImmVal < ER.V.ImmVal; in operator <()
751 return V.ImmVal < ER.V.ImmVal; in operator <()
[all …]
H A DHexagonHardwareLoops.cpp327 unsigned ImmVal; member
337 Contents.ImmVal = v; in CountValue()
356 return Contents.ImmVal; in getImm()
361 if (isImm()) { OS << Contents.ImmVal; } in print()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineOperand.h172 int64_t ImmVal; // For MO_Immediate. member
548 return Contents.ImmVal; in getImm()
666 Contents.ImmVal = immVal; in setImm()
742 void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags = 0);
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DInstruction.h53 int64_t ImmVal; member
81 return ImmVal; in getImm()
108 Op.ImmVal = Val; in createImm()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp3302 if (ImmVal >= -128 && ImmVal < 128) { in SelectSVESignedArithImm()
3316 ImmVal &= 0xFF; in SelectSVEArithImm()
3345 ImmVal = ~ImmVal; in SelectSVELogicalImm()
3350 ImmVal &= 0xFF; in SelectSVELogicalImm()
3351 ImmVal |= ImmVal << 8; in SelectSVELogicalImm()
3352 ImmVal |= ImmVal << 16; in SelectSVELogicalImm()
3353 ImmVal |= ImmVal << 32; in SelectSVELogicalImm()
3357 ImmVal |= ImmVal << 16; in SelectSVELogicalImm()
3358 ImmVal |= ImmVal << 32; in SelectSVELogicalImm()
3362 ImmVal |= ImmVal << 32; in SelectSVELogicalImm()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2746 const MCExpr *ImmVal; in tryParsePrefetch() local
3246 const MCExpr *ImmVal; in tryParseOptionalShiftExtend() local
3474 const MCExpr *ImmVal; in tryParseBarrierOperand() local
3547 const MCExpr *ImmVal; in tryParseBarriernXSOperand() local
3657 const MCExpr *ImmVal; in tryParseVectorIndex() local
3857 ImmVal = AArch64MCExpr::create(ImmVal, RefKind, getContext()); in parseSymbolicImmVal()
4124 const MCExpr *ImmVal; in tryParseGPR64sp0Operand() local
4125 if (getParser().parseExpression(ImmVal) || !isa<MCConstantExpr>(ImmVal) || in tryParseGPR64sp0Operand()
4200 const MCExpr *ImmVal; in parseOptionalMulOperand() local
4361 const MCExpr *ImmVal; in parseOperand() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1742 int64_t ImmVal; in validateTargetOperandClass() local
1744 case MCK_0: ImmVal = 0; break; in validateTargetOperandClass()
1745 case MCK_1: ImmVal = 1; break; in validateTargetOperandClass()
1746 case MCK_2: ImmVal = 2; break; in validateTargetOperandClass()
1747 case MCK_3: ImmVal = 3; break; in validateTargetOperandClass()
1748 case MCK_4: ImmVal = 4; break; in validateTargetOperandClass()
1749 case MCK_5: ImmVal = 5; break; in validateTargetOperandClass()
1750 case MCK_6: ImmVal = 6; break; in validateTargetOperandClass()
1751 case MCK_7: ImmVal = 7; break; in validateTargetOperandClass()
1756 if (Op.isU3Imm() && Op.getImm() == ImmVal) in validateTargetOperandClass()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DImplicitNullChecks.cpp420 int64_t ImmVal; in isSuitableMemoryOp() local
421 if (!TII->getConstValDefinedInReg(*ModifyingMI, RegUsedInAddr, ImmVal)) in isSuitableMemoryOp()
426 APInt ImmValC(RegSizeInBits, ImmVal, true /*IsSigned*/); in isSuitableMemoryOp()
H A DMachineOperand.cpp154 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) { in ChangeToImmediate() argument
160 Contents.ImmVal = ImmVal; in ChangeToImmediate()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp216 uint32_t ImmVal = 0; in getLdStUImm12OpValue() local
219 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
227 return ImmVal; in getLdStUImm12OpValue()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp960 int64_t ImmVal = 0; in parseMembarTag() local
964 if (!Mask->isImm() || !Mask->getImm()->evaluateAsAbsolute(ImmVal) || in parseMembarTag()
965 ImmVal < 0 || ImmVal > 127) { in parseMembarTag()
991 ImmVal |= MaskVal; in parseMembarTag()
997 EVal = MCConstantExpr::create(ImmVal, getContext()); in parseMembarTag()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp753 int64_t ImmVal = Imm; in DecodePCRelLabel19() local
756 if (ImmVal & (1 << (19 - 1))) in DecodePCRelLabel19()
757 ImmVal |= ~((1LL << 19) - 1); in DecodePCRelLabel19()
760 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4)) in DecodePCRelLabel19()
761 Inst.addOperand(MCOperand::createImm(ImmVal)); in DecodePCRelLabel19()
1667 unsigned ImmVal = Imm & 0xFFF; in DecodeAddSubImmShift() local
1687 Inst.addOperand(MCOperand::createImm(ImmVal)); in DecodeAddSubImmShift()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3337 uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm(); in FoldImmediate() local
3360 if (ARM_AM::isSOImmTwoPartVal(ImmVal)) in FoldImmediate()
3362 else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) { in FoldImmediate()
3363 ImmVal = -ImmVal; in FoldImmediate()
3367 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); in FoldImmediate()
3372 if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) in FoldImmediate()
3374 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); in FoldImmediate()
3392 if (ARM_AM::isT2SOImmTwoPartVal(ImmVal)) in FoldImmediate()
3394 else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) { in FoldImmediate()
3395 ImmVal = -ImmVal; in FoldImmediate()
[all …]
H A DARMExpandPseudoInsts.cpp991 unsigned ImmVal = (unsigned)MO.getImm(); in ExpandMOV32BitImm() local
994 if (ARM_AM::isSOImmTwoPartVal(ImmVal)) { // Expand into a movi + orr. in ExpandMOV32BitImm()
999 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); in ExpandMOV32BitImm()
1000 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); in ExpandMOV32BitImm()
1006 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(-ImmVal); in ExpandMOV32BitImm()
1007 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(-ImmVal); in ExpandMOV32BitImm()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1798 Optional<int64_t> ImmVal = getVectorSHLImm(Ty, Src2Reg, MRI); in selectVectorSHL() local
1802 Opc = ImmVal ? AArch64::SHLv2i64_shift : AArch64::USHLv2i64; in selectVectorSHL()
1804 Opc = ImmVal ? AArch64::SHLv4i32_shift : AArch64::USHLv4i32; in selectVectorSHL()
1814 Opc = ImmVal ? AArch64::SHLv8i8_shift : AArch64::USHLv8i8; in selectVectorSHL()
1821 if (ImmVal) in selectVectorSHL()
1822 Shl.addImm(*ImmVal); in selectVectorSHL()
6089 int64_t ImmVal = ValAndVReg->Value.getSExtValue(); in selectExtendedSHL() local
6094 if (!isPowerOf2_32(ImmVal)) in selectExtendedSHL()
6098 ImmVal = Log2_32(ImmVal); in selectExtendedSHL()
6101 if ((ImmVal & 0x7) != ImmVal) in selectExtendedSHL()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetInstrPredicate.td139 int ImmVal = Imm;
146 string ImmVal = Value;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2172 uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue(); in addLiteralImmOperand() local
2173 Inst.addOperand(MCOperand::createImm(ImmVal)); in addLiteralImmOperand()
6737 int64_t ImmVal = 0; in parseHwreg() local
6746 ImmVal = encodeHwreg(HwReg.Id, Offset.Id, Width.Id); in parseHwreg()
6750 } else if (parseExpr(ImmVal, "a hwreg macro")) { in parseHwreg()
6751 if (ImmVal < 0 || !isUInt<16>(ImmVal)) { in parseHwreg()
6759 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg)); in parseHwreg()
6857 int64_t ImmVal = 0; in parseSendMsgOp() local
6866 ImmVal = encodeMsg(Msg.Id, Op.Id, Stream.Id); in parseSendMsgOp()
6870 } else if (parseExpr(ImmVal, "a sendmsg macro")) { in parseSendMsgOp()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp78 bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
226 unsigned ImmVal) const { in isLogicImmOpRedundant()
229 if (Op == AVR::ANDIRdK && ImmVal == 0xff) in isLogicImmOpRedundant()
233 if (Op == AVR::ORIRdK && ImmVal == 0x0) in isLogicImmOpRedundant()

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