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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dinselt-binop.ll7 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 undef>
18 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 -42>
64 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 42>
108 ; CHECK-NEXT: [[BO:%.*]] = shl <2 x i8> <i8 5, i8 2>, [[INS]]
152 ; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]]
174 ; CHECK-NEXT: [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 2>
196 ; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]]
240 ; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> <i8 5, i8 2>, [[INS]]
260 ; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> [[INS]], <i8 5, i8 2>
282 ; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> <i8 5, i8 2>, [[INS]]
[all …]
H A Dinselt-binop-inseltpoison.ll7 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 undef>
18 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 -42>
64 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 42>
108 ; CHECK-NEXT: [[BO:%.*]] = shl <2 x i8> <i8 5, i8 2>, [[INS]]
152 ; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]]
174 ; CHECK-NEXT: [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 2>
196 ; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]]
240 ; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> <i8 5, i8 2>, [[INS]]
260 ; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> [[INS]], <i8 5, i8 2>
282 ; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> <i8 5, i8 2>, [[INS]]
[all …]
H A Dinsert-const-shuf-inseltpoison.ll9 ; CHECK-NEXT: ret <4 x float> [[INS]]
43 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i64 0
44 ; CHECK-NEXT: ret <4 x float> [[INS]]
56 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i64 3
57 ; CHECK-NEXT: ret <4 x float> [[INS]]
70 ; CHECK-NEXT: ret <4 x float> [[INS]]
84 ; CHECK-NEXT: [[ADD:%.*]] = fadd <3 x float> [[SHUF]], [[INS]]
98 ; CHECK-NEXT: [[INS:%.*]] = insertelement <5 x i8> [[SHUF]], i8 42, i64 4
99 ; CHECK-NEXT: ret <5 x i8> [[INS]]
111 ; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> [[SHUF]], i8 42, i64 0
[all …]
H A Dinsert-const-shuf.ll9 ; CHECK-NEXT: ret <4 x float> [[INS]]
43 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i64 0
44 ; CHECK-NEXT: ret <4 x float> [[INS]]
56 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i64 3
57 ; CHECK-NEXT: ret <4 x float> [[INS]]
70 ; CHECK-NEXT: ret <4 x float> [[INS]]
84 ; CHECK-NEXT: [[ADD:%.*]] = fadd <3 x float> [[SHUF]], [[INS]]
98 ; CHECK-NEXT: [[INS:%.*]] = insertelement <5 x i8> [[SHUF]], i8 42, i64 4
99 ; CHECK-NEXT: ret <5 x i8> [[INS]]
111 ; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> [[SHUF]], i8 42, i64 0
[all …]
H A Dinsert-extract-shuffle.ll671 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i64 3
672 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
684 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i64 3
685 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
697 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i64 3
698 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
711 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
726 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
741 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
756 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
[all …]
H A Dinsert-extract-shuffle-inseltpoison.ll48 ; CHECK-NEXT: [[I2:%.*]] = shufflevector <4 x float> [[INS:%.*]], <4 x float> [[TMP1]], <4 x i32…
61 ; CHECK-NEXT: [[I3:%.*]] = shufflevector <4 x float> [[INS:%.*]], <4 x float> [[TMP1]], <4 x i32…
671 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i64 3
672 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
684 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i64 3
685 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
699 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i64 3
700 ; CHECK-NEXT: call void @use(<4 x float> [[INS]])
701 ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x float> [[INS]], <4 x float> [[Y:%.*]], <4 x i32> <i…
714 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.300000e+01, i64 3
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dfcopysign.ll24 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
25 ; 32R2: mthc1 $[[INS]], $f0
36 ; 64R2: dinsu $[[INS:[0-9]+]], $[[EXT]], 63, 1
37 ; 64R2: dmtc1 $[[INS]], $f0
57 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
58 ; 32R2: mtc1 $[[INS]], $f0
H A Dfcopysign-f32-f64.ll26 ; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
27 ; 64R2: mtc1 $[[INS]], $f0
51 ; 64R2: dinsu $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
52 ; 64R2: dmtc1 $[[INS]], $f0
H A Ddins.ll31 ; Testing of selection INS/DINS instruction
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-distribution.mlir10 // CHECK-NEXT: %[[INS:.*]] = vector.insert_map %[[ADD]], %[[ADDV]][%[[ID]]] : vector<1xf32> int…
11 // CHECK-NEXT: return %[[INS]] : vector<32xf32>
27 // CHECK-NEXT: %[[INS:.*]] = vector.insert_map %[[ADD]], %[[ADDV]][%[[ID]]] : vector<1xf32> int…
28 // CHECK-NEXT: return %[[INS]] : vector<32xf32>
111 // CHECK-NEXT: %[[INS:.*]] = vector.insert_map %[[ADD]], %[[ADDV]][%[[ID0]], %[[ID1]]] : vector…
112 // CHECK-NEXT: return %[[INS]] : vector<64x4x32xf32>
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A D2011-09-05-InsertExtractValue.ll36 ; CHECK-NEXT: [[INS:%.*]] = insertvalue { i8, i32 } undef, i32 [[EX]], 1
37 ; CHECK-NEXT: ret { i8, i32 } [[INS]]
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/X86/
H A Dinsert-binop-with-constant.ll30 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> undef, i64 [[LD]], i32 0
31 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i64> [[INS]], <i64 42, i64 -42>
111 ; SSE-NEXT: [[MUL:%.*]] = mul <16 x i8> [[INS]], <i8 3, i8 7, i8 9, i8 11, i8 13, i8 15, i8 17, …
112 ; SSE-NEXT: [[AND:%.*]] = and <16 x i8> [[INS]], [[A1:%.*]]
120 ; AVX-NEXT: [[AND:%.*]] = and <16 x i8> [[INS]], [[A1:%.*]]
156 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> undef, i64 [[LD]], i32 1
157 ; CHECK-NEXT: [[BO:%.*]] = shl <2 x i64> <i64 undef, i64 2>, [[INS]]
168 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, i32 [[A0:%…
171 ; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[INS]], [[A1:%.*]]
207 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> undef, i64 [[LD]], i32 0
[all …]
H A Dinsert-binop-with-constant-inseltpoison.ll30 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LD]], i32 0
31 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i64> [[INS]], <i64 42, i64 -42>
111 ; SSE-NEXT: [[MUL:%.*]] = mul <16 x i8> [[INS]], <i8 3, i8 7, i8 9, i8 11, i8 13, i8 15, i8 17, …
112 ; SSE-NEXT: [[AND:%.*]] = and <16 x i8> [[INS]], [[A1:%.*]]
120 ; AVX-NEXT: [[AND:%.*]] = and <16 x i8> [[INS]], [[A1:%.*]]
156 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LD]], i32 1
157 ; CHECK-NEXT: [[BO:%.*]] = shl <2 x i64> <i64 undef, i64 2>, [[INS]]
168 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, i32 [[A0:%…
171 ; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[INS]], [[A1:%.*]]
207 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LD]], i32 0
[all …]
H A Dscalarize-cmp-inseltpoison.ll173 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LD]], i32 0
174 ; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i64> [[INS]], <i64 42, i64 -42>
H A Dscalarize-cmp.ll173 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i64> undef, i64 [[LD]], i32 0
174 ; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i64> [[INS]], <i64 42, i64 -42>
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/AArch64/
H A Dload-extract-insert-store-scalarization.ll125 ; CHECK-NEXT: [[INS:%.*]] = insertelement <225 x double> [[LV]], double [[SUB]], i64 [[IDX_1]]
126 ; CHECK-NEXT: store <225 x double> [[INS]], <225 x double>* [[A]], align 8
165 ; CHECK-NEXT: [[INS:%.*]] = insertelement <225 x double> [[LV]], double [[SUB]], i64 [[IDX_1]]
166 ; CHECK-NEXT: store <225 x double> [[INS]], <225 x double>* [[A]], align 8
/llvm-project-15.0.7/llvm/test/Transforms/LoopLoadElim/
H A Dsymbolic-stride.ll186 …RWARDED:%.*]] = phi { i32, i8 } [ [[LOAD_INITIAL]], [[FOR_BODY_PH]] ], [ [[INS:%.*]], [[FOR_BODY]]…
196 ; DEFAULT-NEXT: [[INS]] = insertvalue { i32, i8 } undef, i32 [[ADD]], 0
199 ; DEFAULT-NEXT: store { i32, i8 } [[INS]], { i32, i8 }* [[ARRAYIDX_NEXT]], align 4
222 ; NO-VERSION-NEXT: [[INS:%.*]] = insertvalue { i32, i8 } undef, i32 [[ADD]], 0
225 ; NO-VERSION-NEXT: store { i32, i8 } [[INS]], { i32, i8 }* [[ARRAYIDX_NEXT]], align 4
257 …RWARDED:%.*]] = phi { i32, i8 } [ [[LOAD_INITIAL]], [[FOR_BODY_PH]] ], [ [[INS:%.*]], [[FOR_BODY]]…
267 ; THRESHOLD-NEXT: [[INS]] = insertvalue { i32, i8 } undef, i32 [[ADD]], 0
270 ; THRESHOLD-NEXT: store { i32, i8 } [[INS]], { i32, i8 }* [[ARRAYIDX_NEXT]], align 4
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DSelectOptimize.cpp495 SmallPtrSet<const Instruction *, 2> INS; in convertProfitableSIGroups() local
496 INS.insert(ASI.begin(), ASI.end()); in convertProfitableSIGroups()
505 PN->addIncoming(getTrueOrFalseValue(SI, true, INS), TrueBlock); in convertProfitableSIGroups()
506 PN->addIncoming(getTrueOrFalseValue(SI, false, INS), FalseBlock); in convertProfitableSIGroups()
511 INS.erase(SI); in convertProfitableSIGroups()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/instverify/
H A Dins-pos.mir50 %3 = INS killed %2, 32, 4, %0
H A Dins-pos-size.mir50 %3 = INS killed %2, 17, 17, %0
H A Dins-size.mir50 %3 = INS killed %2, 0, 40, %0
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/
H A Dload-insert-store.ll510 ; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
511 ; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[Q:%.*]], align 16
527 ; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
528 ; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[P]], align 16
568 ; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
569 ; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[P]], align 16
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp656 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
664 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
673 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
H A DMipsSEISelDAGToDAG.cpp247 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops); in selectAddE()
258 CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps); in selectAddE()
1027 Opcode = Mips::INS; in trySelect()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dindirect-addressing-si.ll176 ; GCN-DAG: v_mov_b32_e32 v[[INS:[0-9]+]], 0x41880000
178 ; MOVREL: v_movreld_b32_e32 v[[ELT0]], v[[INS]]

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