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Searched refs:IMM (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddivergence-driven-buildvector.ll67 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
90 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
95 ; GFX9: %[[IMM:[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535
106 ; GCN-DAG: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
125 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
126 ; GCN: V_BFI_B32_e64 killed %[[IMM]]
139 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 -65536
159 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 -65536
166 ; GFX9: V_AND_OR_B32_e64 %1, killed %[[IMM]], killed %[[SHR]]
179 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
[all …]
H A Dsdwa-peephole.ll445 ; GFX9: s_mov_b32 s[[IMM:[0-9]+]], 0x141007b
446 ; GFX9: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, s[[IMM]]
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/MachO/
H A Dbad-bind.test10 … --bind %p/Inputs/macho-bind-dylib-special-imm 2>&1 | FileCheck --check-prefix DYLIB-SPECIAL-IMM %s
16 …mp --macho --bind %p/Inputs/macho-bind-set-type-imm 2>&1 | FileCheck --check-prefix SET-TYPE-IMM %s
17 SET-TYPE-IMM: macho-bind-set-type-imm': truncated or malformed object (for BIND_OPCODE_SET_TYPE_IMM…
37 …ind %p/Inputs/macho-bind-add-addr-imm-scaled 2>&1 | FileCheck --check-prefix ADD-ADDR-IMM-SCALED %s
55 …azy-do-bind-add-addr-imm-scaled 2>&1 | FileCheck --check-prefix LAZY-DO-BIND-ADD-ADDR-IMM-SCALED %s
61 …-weak-bind-set-dylib-ordinal-imm 2>&1 | FileCheck --check-prefix WEAK-BIND-SET-DYLIB-ORDINAL-IMM %s
67 …-weak-bind-set-dylib-special-imm 2>&1 | FileCheck --check-prefix WEAK-BIND-SET-DYLIB-SPECIAL-IMM %s
70 …--rebase %p/Inputs/macho-rebase-set-type-imm 2>&1 | FileCheck --check-prefix REBASE-SET-TYPE-IMM %s
71 REBASE-SET-TYPE-IMM: macho-rebase-set-type-imm': truncated or malformed object (for REBASE_OPCODE_S…
85 …puts/macho-rebase-add-addr-imm-scaled 2>&1 | FileCheck --check-prefix REBASE-ADD-ADDR-IMM-SCALED %s
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/arm/
H A Dudivsi3.S183 #define IMM # macro
199 lsls r2, r1, IMM shift; \
214 cmp r0, r1, lsl IMM shift; \
216 WIDE(addhs) r3, r3, IMM (1 << shift); \
217 WIDE(subhs) r0, r0, r1, lsl IMM shift
H A Dudivmodsi4.S110 #define IMM # macro
113 cmp r0, r1, lsl IMM shift; \
115 WIDE(addhs) r3, r3, IMM (1 << shift); \
116 WIDE(subhs) r0, r0, r1, lsl IMM shift
H A Dumodsi3.S102 #define IMM # macro
105 cmp r0, r1, lsl IMM shift; \
107 WIDE(subhs) r0, r0, r1, lsl IMM shift
/llvm-project-15.0.7/lld/test/ELF/
H A Dpr34660.s10 # IMM = hex(65540) = 0x10004
12 # As the relocation is PC-relative, IMM + PC = 0x20004 which is the VA of the
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dvargs.ll11 ; CHECK: sub sp, #[[IMM:[0-9]+]]
39 ; CHECK: add sp, #[[IMM]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcmov.ll358 ; 32-CMP-DAG: lui $[[IMM:[0-9]+]], 65535
359 ; 32-CMP-DAG: ori $[[IMM]], $[[IMM]], 32766
375 ; 64-CMP-DAG: lui $[[IMM:[0-9]+]], 65535
376 ; 64-CMP-DAG: ori $[[IMM]], $[[IMM]], 32766
377 ; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[IMM]], $4
667 ; 32-CMP-DAG: lui $[[IMM:[0-9]+]], 65535
668 ; 32-CMP-DAG: ori $[[IMM]], $[[IMM]], 32766
684 ; 64-CMP-DAG: lui $[[IMM:[0-9]+]], 65535
685 ; 64-CMP-DAG: ori $[[IMM]], $[[IMM]], 32766
686 ; 64-CMP-DAG: sltu $[[R0:[0-9]+]], $[[IMM]], $4
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td41 /// 1 1 1 0 | REG/IMM | D | SIZE |R/I| OP | REG
46 // REG/IMM
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td77 // Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
91 // Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
141 // Format< OP[6] | SOP[5] | RX[5] | 00000000000000[14] | IMM[2] >
195 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] >
262 // Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
280 // Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5]>
386 // Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
469 // Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | 00000 >
486 // Format< OP[6] | IMM[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5]>
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Drlwinm_rldicl_to_andi.mir186 ; CHECK-LATE: li [[IMM:[0-9]+]], 1
187 ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
355 ; CHECK-LATE: li [[IMM:[0-9]+]], 1
356 ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrP10.td29 // * IMM - immediate (where signedness matters,
48 // The operand is an 8-bit immediate (IMM), the destination (XT)
303 // X-Form: [PO T IMM VRB XO TX]
309 bits<5> IMM;
313 let Inst{11-15} = IMM;
327 bits<8> IMM;
337 let Inst{24-31} = IMM;
523 bits<3> IMM;
532 let Inst{29-31} = IMM;
1632 vsrc:$XC, u8imm:$IMM),
[all …]
H A DPPCInstrFormats.td1981 bits<5> IMM;
1986 let Inst{11-15} = IMM;
H A DPPCInstrVSX.td3882 def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)),
3883 (v4i32 (XXINSERTW $A, $B, imm:$IMM))>;
3884 def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)),
3885 (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>;
H A DPPCInstrAltivec.td846 let IMM=-1 in {
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZPatterns.td40 // respectively. MODE is the addressing mode and IMM is the type
49 // memory location. IMM is the type of the second operand.
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSMInstructions.td865 // 1. IMM offset
871 // 2. 32-bit IMM offset on CI
884 // 4. SGPR+IMM offset
906 // 2. 32-bit IMM offset on CI
/llvm-project-15.0.7/llvm/test/FileCheck/
H A Dnumeric-expression.txt268 USE IMPL FMT IMPL MATCH UNSIGNED IMM
270 CHECK-LABEL: USE IMPL FMT IMPL MATCH UNSIGNED IMM
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleR52.td298 (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
299 "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
H A DARMScheduleSwift.td366 (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
367 "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dsmem_gfx9.txt326 # Decoding of OFFSET>127 with IMM=0
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Datomic-ops-lse.ll1545 ; CHECK: mov w[[IMM:[0-9]+]], #1
1548 ; CHECK: ldaddalb w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
1568 ; CHECK: mov w[[IMM:[0-9]+]], #1
1571 ; CHECK: ldaddalh w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
1591 ; CHECK: mov w[[IMM:[0-9]+]], #1
1594 ; CHECK: ldaddal w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
1614 ; CHECK: mov w[[IMM:[0-9]+]], #1
1617 ; CHECK: ldaddal x[[IMM]], x[[NEW:[0-9]+]], [x[[ADDR]]]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td1433 Operand IMMType, SDNode IMM, list<Predicate> Pred> {
1440 [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
1444 string OpcStr, PatFrag IntOp, Operand IMMType, SDNode IMM,
1447 IntOp, IMMType, IMM, Pred>;
1449 IntOp, IMMType, IMM, Pred>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6868 const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]); in shouldOmitCCOutOperand() local
6869 if (IMM.isT2SOImm() || IMM.isT2SOImmNeg()) in shouldOmitCCOutOperand()
6871 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IMM.getImm())) { in shouldOmitCCOutOperand()