Lines Matching refs:IMM

67 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
68 ; GCN: %[[AND:[0-9]+]]:sreg_32 = S_AND_B32 killed %{{[0-9]+}}, killed %[[IMM]]
90 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
91 ; GCN: %[[AND:[0-9]+]]:vgpr_32 = V_AND_B32_e64 %0, killed %[[IMM]], implicit $exec
95 ; GFX9: %[[IMM:[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535
96 ; GFX9: %[[AND:[0-9]+]]:vgpr_32 = V_AND_B32_e64 killed %[[IMM]]
106 ; GCN-DAG: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
107 ; GCN-DAG: %[[AND:[0-9]+]]:sreg_32 = S_AND_B32 killed %{{[0-9]+}}, killed %[[IMM]]
125 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
126 ; GCN: V_BFI_B32_e64 killed %[[IMM]]
139 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 -65536
140 ; GCN: %[[AND:[0-9]+]]:sreg_32 = S_AND_B32 killed %{{[0-9]+}}, killed %[[IMM]]
159 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 -65536
160 ; GCN: %[[AND:[0-9]+]]:vgpr_32 = V_AND_B32_e64 %1, killed %[[IMM]], implicit $exec
165 ; GFX9: %[[IMM:[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -65536, implicit $exec
166 ; GFX9: V_AND_OR_B32_e64 %1, killed %[[IMM]], killed %[[SHR]]
179 ; GCN: %[[IMM:[0-9]+]]:sreg_32 = S_MOV_B32 65535
180 ; GCN: %[[AND:[0-9]+]]:sreg_32 = S_AND_B32 killed %{{[0-9]+}}, killed %[[IMM]]
208 ; GFX9: %[[IMM:[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535
209 ; GFX9: %[[AND:[0-9]+]]:vgpr_32 = V_AND_B32_e64 killed %[[IMM]]