| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 805 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
813 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
821 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
845 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
856 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
873 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
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| H A D | HexagonPatterns.td | 872 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
882 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
1493 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)),
1497 (Combinew (M2_mpy_up (HiReg $Rs), (HiReg $Rt)),
1502 (Combinew (S2_vtrunohb (M5_vmpybuu (HiReg $Rss), (HiReg $Rtt))),
1521 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (HiReg $Rss), (HiReg $Rtt))>;
1658 (HiReg $Rss),
1662 (HiReg $Rss),
1663 (HiReg $Rtt)),
1736 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)),
[all …]
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| H A D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 1129 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
1131 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| H A D | AVRRegisterInfo.cpp | 286 Register &HiReg) const { in splitReg()
290 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1988 .addReg(HiReg); in selectG_TRUNC()
1991 .addReg(HiReg) in selectG_TRUNC()
2236 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
2241 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg) in selectG_CONSTANT()
2247 .addReg(HiReg) in selectG_CONSTANT()
2297 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), HiReg) in selectG_FNEG()
2305 .addReg(HiReg) in selectG_FNEG()
2346 .addReg(HiReg) in selectG_FABS()
2611 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg) in selectG_PTRMASK()
2633 MaskedHi = HiReg; in selectG_PTRMASK()
[all …]
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| H A D | SILoadStoreOptimizer.cpp | 180 Register HiReg; member
1835 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || in computeBase()
1862 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg) in computeBase()
1965 Addr.Base.HiReg = BaseHi.getReg(); in processBaseWithConstOffset()
2012 LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", " in promoteConstantOffsetToImm()
2070 MAddrNext.Base.HiReg != MAddr.Base.HiReg || in promoteConstantOffsetToImm()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
876 .addReg(HiReg); in expandBuildPairF64()
881 .addReg(HiReg); in expandBuildPairF64()
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| H A D | MipsISelLowering.cpp | 2954 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32() local
2955 assert(HiReg); in CC_MipsO32()
2957 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); in CC_MipsO32()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5211 unsigned LoReg, HiReg; in Select() local
5225 HiReg = X86::EDX; in Select()
5235 HiReg = X86::RDX; in Select()
5311 assert(HiReg && "Register for high half is not defined!"); in Select()
5350 unsigned LoReg, HiReg, ClrReg; in Select() local
5355 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
5359 LoReg = X86::AX; HiReg = X86::DX; in Select()
5364 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; in Select()
5368 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
5465 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) { in Select()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1974 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
1978 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
1980 --HiReg; in CMSEPushCalleeSaves()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 9802 Register HiReg = MI.getOperand(1).getReg(); in emitReadCycleWidePseudo() local
9806 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg) in emitReadCycleWidePseudo()
9817 .addReg(HiReg) in emitReadCycleWidePseudo()
9838 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
9854 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
9873 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
9888 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7495 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
7503 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12359 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
12361 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
12368 .addReg(HiReg) in EmitInstrWithCustomInserter()
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