| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | warn-bitfield-enum-conversion.cpp | 4 enum TwoBits { Hi1 = 3 } two_bits; enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVAsmBackend.cpp | 440 unsigned Hi1 = (Value >> 11) & 0x1; in adjustFixupValue() local
447 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7); in adjustFixupValue()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 750 SDValue Hi1 = Node->getOperand(1); in trySelect() local
755 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 850 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in SelectADD_SUB_I64() local
874 SDValue(Hi1, 0), in SelectADD_SUB_I64()
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| H A D | AMDGPUInstructionSelector.cpp | 359 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB() local
370 .add(Hi1) in selectG_ADD_SUB()
382 .add(Hi1) in selectG_ADD_SUB()
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| H A D | SIISelLowering.cpp | 4601 SDValue Lo1, Hi1; in splitBinaryVectorOp() local
4602 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1); in splitBinaryVectorOp()
4608 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, in splitBinaryVectorOp()
4628 SDValue Lo1, Hi1; in splitTernaryVectorOp() local
4629 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1); in splitTernaryVectorOp()
4638 SDValue OpHi = DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, in splitTernaryVectorOp()
8789 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); in LowerSELECT() local
8791 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1); in LowerSELECT()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 4918 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
4932 (AND Shift1.Left, MaskValues.Hi1));
4986 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32));
4995 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA);
5004 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1));
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 3524 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; in SplitVecOp_VSETCC() local
3527 GetSplitVector(N->getOperand(1), Lo1, Hi1); in SplitVecOp_VSETCC()
3536 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
3545 HiRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Hi0, Hi1, in SplitVecOp_VSETCC()
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| H A D | TargetLowering.cpp | 4706 SDValue Lo0, Lo1, Hi0, Hi1; in SimplifySetCC() local
4708 IsConcat(N0.getOperand(1), Lo1, Hi1)) { in SimplifySetCC()
4710 DAG.getNode(N0.getOpcode(), dl, OpVT, Hi0, Hi1)); in SimplifySetCC()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9270 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); in isExtendedBUILD_VECTOR() local
9271 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) in isExtendedBUILD_VECTOR()
9275 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) in isExtendedBUILD_VECTOR()
9278 if (Hi0->isZero() && Hi1->isZero()) in isExtendedBUILD_VECTOR()
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