| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | atomics-hw-remarks-gfx90a.ll | 4 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope system due to…
5 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope agent due to …
6 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope workgroup due…
7 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope wavefront due…
8 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope singlethread …
9 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope agent-one-as …
10 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope workgroup-one…
11 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope wavefront-one…
12 ; GFX90A-HW: Hardware instruction generated for atomic fadd operation at memory scope singlethread-…
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| /llvm-project-15.0.7/clang/test/CodeGenOpenCL/ |
| H A D | atomics-unsafe-hw-remarks-gfx90a.cl | 30 // GFX90A-HW-REMARK: Hardware instruction generated for atomic fadd operation at memory scope workg…
31 // GFX90A-HW-REMARK: Hardware instruction generated for atomic fadd operation at memory scope agent…
32 // GFX90A-HW-REMARK: Hardware instruction generated for atomic fadd operation at memory scope wavef…
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| /llvm-project-15.0.7/llvm/include/llvm/MCA/ |
| H A D | Context.h | 52 SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware; variable
65 Hardware.push_back(std::move(H)); in addHardwareUnit()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PfmCounters.td | 1 //===-- AArch64PfmCounters.td - AArch64 Hardware Counters --*- tablegen -*-===//
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCPfmCounters.td | 1 //===-- PPCPfmCounters.td - PPC Hardware Counters ----------*- tablegen -*-===//
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| H A D | PPCInstrHTM.td | 1 //===-- PPCInstrHTM.td - The PowerPC Hardware Transactional Memory -*-===//
9 // This file describes the Hardware Transactional Memory extension to the
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsPfmCounters.td | 1 //===-- MipsPfmCounters.td - Mips Hardware Counters --------*- tablegen -*-===//
|
| H A D | MipsRegisterInfo.td | 78 // Mips Hardware Registers
218 // Hardware registers
457 // Hardware registers
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| /llvm-project-15.0.7/lldb/unittests/TestingSupport/Host/ |
| H A D | NativeProcessTestUtils.h | 64 bool Hardware) /*override*/ { in SetBreakpoint() argument
65 if (Hardware) in SetBreakpoint()
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | pr42492.ll | 5 ; Check we don't assert and this is not a Hardware Loop
|
| H A D | O3-pipeline.ll | 79 ; CHECK-NEXT: Hardware Loop Insertion
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | Sanitizers.def | 52 // Hardware-assisted AddressSanitizer
55 // Kernel Hardware-assisted AddressSanitizer (KHWASan)
|
| H A D | MSP430Target.def | 235 // With 32 Bit Hardware Multiplier
|
| /llvm-project-15.0.7/mlir/docs/Dialects/ |
| H A D | Vector.md | 48 almost 1-1 with the HW ISA. This is referred to as the Hardware Vector
66 2. `Virtual Vector -> Hardware Vector` lowering is specified as a set of MLIR
68 3. `Hardware Vector -> LLVM` lowering is a mechanical process that is written
70 Hardware Vector` ops generation as closely as possible.
83 ### Hardware Vector Ops
85 Hardware Vector Ops are implemented as one dialect per target. For internal
154 ### Virtual Vector to Hardware Vector Lowering
167 ### Hardware as `vector` Machines of Minimum Granularity
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| /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/ |
| H A D | hwloop-phi-subreg.ll | 5 ; new preheader is created in the Hardware Loop pass.
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| /llvm-project-15.0.7/llvm/lib/Support/ |
| H A D | Host.cpp | 170 StringRef Hardware; in getHostCPUNameForARM() local
176 Hardware = Lines[I].substr(8).ltrim("\t :"); in getHostCPUNameForARM()
184 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) in getHostCPUNameForARM()
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| /llvm-project-15.0.7/lldb/include/lldb/Breakpoint/ |
| H A D | Breakpoint.h | 92 enum class OptionNames : uint32_t { Names = 0, Hardware, LastOptionName }; enumerator
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | MemTagSanitizer.rst | 12 functionality is planned but not implemented. Hardware capable of
|
| H A D | CompilerWriterInfo.rst | 13 Hardware chapter
|
| H A D | GettingStartedVS.rst | 37 Hardware section in Requirements
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPU.td | 104 "Hardware supports unaligned global loads and stores"
122 "Hardware supports unaligned local and region loads and stores"
146 "Hardware supports XNACK"
628 "Hardware supports SRAMECC"
791 "Hardware automatically inserts waitcnt before barrier"
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| /llvm-project-15.0.7/lldb/source/Breakpoint/ |
| H A D | Breakpoint.cpp | 100 Breakpoint::GetKey(OptionNames::Hardware), m_hardware); in SerializeToStructuredData()
198 Breakpoint::GetKey(OptionNames::Hardware), hardware); in CreateFromStructuredData()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86PfmCounters.td | 1 //===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
|
| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | O3-pipeline.ll | 60 ; CHECK-NEXT: Hardware Loop Insertion
|
| /llvm-project-15.0.7/clang/docs/ |
| H A D | HardwareAssistedAddressSanitizerDesign.rst | 2 Hardware-assisted AddressSanitizer Design Documentation
|