[X86] Add RDPRU instruction CPUID bit masks

As mentioned on D128934 - we weren't including the CPUID bit handling for the RDPRU instruction

AMD's APMv3 (24594) lists it as CPUID Fn8000_0008_EBX Bit

[X86] Add RDPRU instruction CPUID bit masks

As mentioned on D128934 - we weren't including the CPUID bit handling for the RDPRU instruction

AMD's APMv3 (24594) lists it as CPUID Fn8000_0008_EBX Bit#4

(cherry picked from commit 08a880509e4f7ca8d346dce42fe7528c3a33f22c)

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[Support] Handle SPARC in sys::getHostCPUName

While working on D118450 <https://reviews.llvm.org/D118450>, I noticed that
`sys::getHostCPUName` lacks SPARC support.

This patch implements it. The c

[Support] Handle SPARC in sys::getHostCPUName

While working on D118450 <https://reviews.llvm.org/D118450>, I noticed that
`sys::getHostCPUName` lacks SPARC support.

This patch implements it. The code is taken from/inspired by GCC's
`gcc/config/sparc/driver-sparc.cc`. There's one caveat: since LLVM, unlike
GCC, doesn't support the SPARC-M7, -S7, and -M8 CPUs, I map all those to
the latest supported one (UltraSparc T4/`niagara4`).

Tested on `sparcv9-sun-solaris2.11` and `sparc64-unknown-linux-gnu` by
running `savcov --version` on

- Netra SPARC S7-2 (SPARC-S7, Solaris 11.4)
- SPARC T5-2 (SPARC T5, Solaris 11.4)
- SPARC Enterprise T5220 (UltraSPARC T2, Solaris 11.3)
- SPARC T5 (UltraSPARC T5, Debian sid)
- SPARC T3 (UltraSPARC T3, Debian sid)
- SPARC Enterprise T5220 (Debian sid)

Differential Revision: https://reviews.llvm.org/D130272

(cherry picked from commit 979ddfff37d7e3bf258c2e5cbdc272fcb44c15f0)

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[RISCV] Support getHostCpuName for sifive-u74

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D123978

[AArch64] Add native CPU detection for Ampere1

Map the IMPLEMENTOR ID 0xc0 (Ampere Computing) and CPU ID 0xac3
(Ampere1) to ampere1.

Differential Revision: https://reviews.llvm.org/D117111

Support z16 processor name

The recently announced IBM z16 processor implements the architecture
already supported as "arch14" in LLVM. This patch adds support for
"z16" as an alternate architecture

Support z16 processor name

The recently announced IBM z16 processor implements the architecture
already supported as "arch14" in LLVM. This patch adds support for
"z16" as an alternate architecture name for arch14.

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reland: [AArch64] Add support for -march=native for Apple M1 CPU

This reverts commit fc3cdd0b295a04c38f01b391ae414553963e33b9.

The issue was imports being scoped to specific architectures for Apple

reland: [AArch64] Add support for -march=native for Apple M1 CPU

This reverts commit fc3cdd0b295a04c38f01b391ae414553963e33b9.

The issue was imports being scoped to specific architectures for Apple
platforms.

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Revert "[AArch64] Add support for -march=native for Apple M1 CPU"

This reverts commit fcca10c69aaab539962d10fcc59a5f074b73b0de.

[AArch64] Add support for -march=native for Apple M1 CPU

This improves the getHostCPUName check for Apple M1 CPUs, which
previously would always be considered cyclone instead. This also enables
`-ma

[AArch64] Add support for -march=native for Apple M1 CPU

This improves the getHostCPUName check for Apple M1 CPUs, which
previously would always be considered cyclone instead. This also enables
`-march=native` support when building on M1 CPUs which would previously
fail. This isn't as sophisticated as the X86 CPU feature checking which
consults the CPU via getHostCPUFeatures, but this is still better than
before. This CPU selection could also be invalid if this was run on an
iOS device instead, ideally we can improve those cases as they come up.

Differential Revision: https://reviews.llvm.org/D119788

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Missing include in Support/Host.cpp under __MVS__

[X86] Fix AMD Znver3 model checks

While `-march=` is correctly detected as `znver3` for the cpu,
apparently the model check is incorrect:
```
$ lscpu
Architecture: x86_64
CPU op-mode(s)

[X86] Fix AMD Znver3 model checks

While `-march=` is correctly detected as `znver3` for the cpu,
apparently the model check is incorrect:
```
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Address sizes: 48 bits physical, 48 bits virtual
Byte Order: Little Endian
CPU(s): 32
On-line CPU(s) list: 0-31
Vendor ID: AuthenticAMD
Model name: AMD Ryzen 9 5950X 16-Core Processor
CPU family: 25
Model: 33
Thread(s) per core: 2
Core(s) per socket: 16
Socket(s): 1
Stepping: 0
Frequency boost: disabled
CPU max MHz: 6017.8462
CPU min MHz: 2200.0000
BogoMIPS: 8050.07
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse
3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_p
state ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbn
oinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
Virtualization features:
Virtualization: AMD-V
Caches (sum of all):
L1d: 512 KiB (16 instances)
L1i: 512 KiB (16 instances)
L2: 8 MiB (16 instances)
L3: 64 MiB (2 instances)
NUMA:
NUMA node(s): 1
NUMA node0 CPU(s): 0-31
Vulnerabilities:
Itlb multihit: Not affected
L1tf: Not affected
Mds: Not affected
Meltdown: Not affected
Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl
Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Spectre v2: Mitigation; Retpolines, IBPB conditional, IBRS_FW, STIBP always-on, RSB filling
Srbds: Not affected
Tsx async abort: Not affected
```

Model is 33 (0x21), while the code was expecting it to be `0x00 .. 0x1F`.
https://github.com/torvalds/linux/blob/v5.17-rc8/drivers/hwmon/k10temp.c#L432-L453 agrees.
I'm not sure if other ranges listed here should also be accepted.

I noticed this while implementing CPU model detection
for halide (https://github.com/halide/Halide/pull/6648)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121708

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Cleanup include: TableGen

This also includes a few cleanup from Support.

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.l

Cleanup include: TableGen

This also includes a few cleanup from Support.

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121331

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[Support][AArch64] Detect a few more host CPU features on AArch64

Add detecton for lse, sve and sve2 on linux

Differential Revision: https://reviews.llvm.org/D119435

[ARM] Add Cortex-X1C Support for Clang and LLVM

This patch upstreams support for the Arm-v8 Cortex-X1C processor for AArch64 and
ARM.

For more information, see:
- https://community.arm.com/arm-comm

[ARM] Add Cortex-X1C Support for Clang and LLVM

This patch upstreams support for the Arm-v8 Cortex-X1C processor for AArch64 and
ARM.

For more information, see:
- https://community.arm.com/arm-community-blogs/b/announcements/posts/arm-cortex-x1c
- https://developer.arm.com/documentation/101968/0002/Functional-description/Technical-overview/Components

The following people contributed to this patch:
- Simon Tatham
- Ties Stuij

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D117202

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[AArch64] Add native CPU detection for Neoverse-V1.

Map Main ID part number 0xd40 to neoverse-v1, as described in the
Neoverse-V1 Technical Reference Manual:

https://developer.arm.com/documentation

[AArch64] Add native CPU detection for Neoverse-V1.

Map Main ID part number 0xd40 to neoverse-v1, as described in the
Neoverse-V1 Technical Reference Manual:

https://developer.arm.com/documentation/101427/0101/Register-descriptions/AArch64-system-registers/MIDR-EL1--Main-ID-Register--EL1

Differential Revision: https://reviews.llvm.org/D117207

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[llvm] Use nullptr instead of 0 (NFC)

Identified with modernize-use-nullptr.

[Support] Define sys::getHostCPUName for RISC-V

The RISCV target doesn't define a "generic" cpu, only "generic-rv32" and
"generic-rv64". Define sys::getHostCPUName for RISC-V that returns the
corre

[Support] Define sys::getHostCPUName for RISC-V

The RISCV target doesn't define a "generic" cpu, only "generic-rv32" and
"generic-rv64". Define sys::getHostCPUName for RISC-V that returns the
correct cpu for the host.

Reviewed By: craig.topper, MaskRay

Differential Revision: https://reviews.llvm.org/D105274

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[X86] Add CRC32 feature.

d8faf03807ac implemented general-regs-only for X86 by disabling all features
with vector instructions. But the CRC32 instruction in SSE4.2 ISA, which uses
only GPRs, also be

[X86] Add CRC32 feature.

d8faf03807ac implemented general-regs-only for X86 by disabling all features
with vector instructions. But the CRC32 instruction in SSE4.2 ISA, which uses
only GPRs, also becomes unavailable. This patch adds a CRC32 feature for this
instruction and allows it to be used with general-regs-only.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D105462

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[X86] AVX512FP16 instructions enabling 1/6

1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.co

[X86] AVX512FP16 instructions enabling 1/6

1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105263

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[X86] Support auto-detect for tigerlake and alderlake

Differential Revision: https://reviews.llvm.org/D107245

[SystemZ] Add support for new cpu architecture - arch14

This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new pr

[SystemZ] Add support for new cpu architecture - arch14

This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch14 as host processor.
- Assembler/disassembler support for new instructions.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining __VEC__ == 10304.

Note: No currently available Z system supports the arch14
architecture. Once new systems become available, the
official system name will be added as supported -march name.

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[SystemZ] Fix invalid assumption in getCPUNameFromS390Model

Code in getCPUNameFromS390Model currently assumes that the
numerical value of the model number always increases with
future hardware. Whi

[SystemZ] Fix invalid assumption in getCPUNameFromS390Model

Code in getCPUNameFromS390Model currently assumes that the
numerical value of the model number always increases with
future hardware. While this has happened to be the case
with the last few machines, it is not guaranteed -- that
assumption was violated with (much) older machines, and
it can be violated again with future machines.

Fix by explicitly listing model numbers for all supported
machine models.

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[Support] Get correct number of physical cores on Apple Silicon

Fix a bug that `computeHostNumPhysicalCores` is fallback to default
unknown when building for Apple Silicon macs.

rdar://80533675

Re

[Support] Get correct number of physical cores on Apple Silicon

Fix a bug that `computeHostNumPhysicalCores` is fallback to default
unknown when building for Apple Silicon macs.

rdar://80533675

Reviewed By: arphaman

Differential Revision: https://reviews.llvm.org/D106012

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[SystemZ][z/OS] Implement getHostCPUName for z/OS

- Currently, the host cpu information is not easily available on z/OS as in other platforms.
- This information is stored in the Communications Vect

[SystemZ][z/OS] Implement getHostCPUName for z/OS

- Currently, the host cpu information is not easily available on z/OS as in other platforms.
- This information is stored in the Communications Vector Table (https://www.ibm.com/docs/en/zos/2.2.0?topic=information-cvt-mapping)

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D102793

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[X86] Support -march=rocketlake

Reviewed By: skan, craig.topper, MaskRay

Differential Revision: https://reviews.llvm.org/D100085

[llvm] Fix thinko in getVendorSignature(), where expected values of ECX and EDX were flipped for the AMD case.

Follow up to D97504

Differential Revision: https://reviews.llvm.org/D98322