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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Datomics-hw-remarks-gfx90a.ll14 ; GFX90A-HW-LABEL: atomic_add_unsafe_hw:
15 ; GFX90A-HW: ds_add_f64 v2, v[0:1]
16 ; GFX90A-HW: s_endpgm
25 ; GFX90A-HW: s_endpgm
34 ; GFX90A-HW: s_endpgm
43 ; GFX90A-HW: s_endpgm
52 ; GFX90A-HW: s_endpgm
61 ; GFX90A-HW: s_endpgm
70 ; GFX90A-HW: s_endpgm
79 ; GFX90A-HW: s_endpgm
[all …]
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Datomics-unsafe-hw-remarks-gfx90a.cl3 // RUN: FileCheck %s --check-prefix=GFX90A-HW
7 // RUN: FileCheck %s --check-prefix=GFX90A-HW-REMARK
30 // GFX90A-HW-REMARK: Hardware instruction generated for atomic fadd operation at memory scope workg…
31 // GFX90A-HW-REMARK: Hardware instruction generated for atomic fadd operation at memory scope agent…
33 // GFX90A-HW-REMARK: global_atomic_add_f32 v0, v[0:1], v2, off glc
34 // GFX90A-HW-REMARK: global_atomic_add_f32 v0, v[0:1], v2, off glc
35 // GFX90A-HW-REMARK: global_atomic_add_f32 v0, v[0:1], v2, off glc
36 // GFX90A-HW-LABEL: @atomic_unsafe_hw
37 // GFX90A-HW: atomicrmw fadd float addrspace(1)* %{{.*}}, float %{{.*}} syncscope("workgroup-one-…
38 // GFX90A-HW: atomicrmw fadd float addrspace(1)* %{{.*}}, float %{{.*}} syncscope("agent-one-as")…
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/llvm-project-15.0.7/llvm/unittests/ExecutionEngine/Orc/
H A DMemoryMapperTest.cpp80 std::string HW = "Hello, world!"; in TEST() local
84 char *WA1 = Mapper->prepare(Mem1->Start, HW.size() + 1); in TEST()
85 std::strcpy(static_cast<char *>(WA1), HW.c_str()); in TEST()
93 Seg1.ContentSize = HW.size(); in TEST()
109 char *WA2 = Mapper->prepare(Mem1->Start + PageSize, HW.size() + 1); in TEST()
110 std::strcpy(static_cast<char *>(WA2), HW.c_str()); in TEST()
117 Seg2.ContentSize = HW.size(); in TEST()
138 EXPECT_EQ(HW, std::string(static_cast<char *>(Init1->toPtr<char *>()))); in TEST()
162 char *WA = Mapper->prepare(Mem2->Start, HW.size() + 1); in TEST()
163 std::strcpy(static_cast<char *>(WA), HW.c_str()); in TEST()
[all …]
H A DSimpleExecutorMemoryManagerTest.cpp41 std::string HW = "Hello, world!"; in TEST() local
51 {HW.data(), HW.size() + 1}}); in TEST()
71 EXPECT_EQ(HW, std::string(Mem->toPtr<const char *>())); in TEST()
H A DSimplePackedSerializationTest.cpp126 const char *HW = "Hello, world!"; in TEST() local
127 spsSerializationRoundTrip<SPSString>(StringRef(HW)); in TEST()
/llvm-project-15.0.7/compiler-rt/lib/builtins/
H A Dfp_div_impl.inc27 #define HW (typeWidth / 2)
29 #define loMask (REP_C(-1) >> HW)
129 // <= abs(e_n) + 2 * 2^-HW
157 // so x0 fits to UQ0.HW without wrapping.
190 // Now, we should multiply UQ0.HW and UQ1.(HW-1) numbers, naturally
232 rep_t x_UQ0 = (rep_t)x_UQ0_hw << HW;
264 // x_UQ0 = x_UQ0_hw * 2^HW - 1
265 // x_UQ0 * b_UQ1 = (x_UQ0_hw * 2^HW) * (b_UQ1_hw * 2^HW + blo) - b_UQ1
276 rep_t hi_corr = corr_UQ1 >> HW;
277 // x_UQ0 * corr_UQ1 = (x_UQ0_hw * 2^HW) * (hi_corr * 2^HW + lo_corr) - corr_UQ1
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/llvm-project-15.0.7/mlir/docs/Dialects/
H A DVector.md48 almost 1-1 with the HW ISA. This is referred to as the Hardware Vector
171 `vector` types that are multiples of a "good" `vector` size so the HW can
173 `vector<8x8x8x16xf32>` when HW `vector` size is say `vector<4x8xf32>`).
182 3. Other accelerators: n-D `vector` as first-class citizens in the HW.
361 to hold a vector that is larger than the HW.
368 #### HW Vectors and Implications on the SW and the Programming Model
372 vector registers. We note that multiple HW vendors are in the process of
377 HW `vector` size and `n >= 2`. In this context, most HW exhibit a vector
379 sizes of the SW vector abstraction and the HW vector sizes and number of
381 `1-D` HW vector registers + memory locations at a given point in time.
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DHwModeSelect.td4 // classes that are then used to select a value based on the HW mode.
5 // It contains a list of HW modes, and a derived class should provide a
/llvm-project-15.0.7/llvm/lib/DebugInfo/PDB/Native/
H A DTpiStreamBuilder.cpp197 BinaryStreamWriter HW(*HVS); in commit() local
199 if (auto EC = HW.writeStreamRef(*HashValueStream)) in commit()
204 if (auto EC = HW.writeObject(IndexOffset)) in commit()
/llvm-project-15.0.7/compiler-rt/lib/orc/unittests/
H A Dsimple_packed_serialization_test.cpp129 const char *HW = "Hello, world!"; in TEST() local
130 blobSerializationRoundTrip<SPSString, string_view>(string_view(HW)); in TEST()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td500 def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>;
501 def : InstRW<[P5600WriteMSALongInt], (instregex "^MADD_Q_[HW]$")>;
502 def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>;
503 def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>;
504 def : InstRW<[P5600WriteMSALongInt], (instregex "^MULR_Q_[HW]$")>;
505 def : InstRW<[P5600WriteMSALongInt], (instregex "^MUL_Q_[HW]$")>;
H A DMipsScheduleGeneric.td1579 def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>;
1580 def : InstRW<[GenericWriteMSALongInt], (instregex "^MADD_Q_[HW]$")>;
1581 def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>;
1582 def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>;
1583 def : InstRW<[GenericWriteMSALongInt], (instregex "^MULR_Q_[HW]$")>;
1584 def : InstRW<[GenericWriteMSALongInt], (instregex "^MUL_Q_[HW]$")>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A DO3-pipeline.ll35 ; CHECK-NEXT: Falkor HW Prefetch Fix
204 ; CHECK-NEXT: Falkor HW Prefetch Fix Late Phase
H A Dfalkor-hwpf-fix.mir309 # Check that we handle case of strided load with no HW prefetcher tag correctly.
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/AArch64/
H A Dfalkor-prefetch.ll4 ; Check that loop unroller doesn't exhaust HW prefetcher resources.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td420 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
423 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
427 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
428 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedKryoDetails.td1510 (instregex "LDRS(BW|BX|HW|HX|W)ui")>;
1516 (instregex "LDRS(BW|BX|HW|HX|W)ro(W|X)")>;
1522 (instregex "LDRS(BW|BX|HW|HX|W)(post|pre)")>;
1540 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
H A DAArch64SchedAmpere1.td966 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
970 (instregex "LDURS(BW|BX|HW|HX|W)i")>;
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrFormats.td46 /// VLIndex is the index of VL register in MI's operands. The HW instruction
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td32 // TODO - tune this on real HW once it arrives. For now, we will use the same
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td22 // A string representing subtarget features that turn on this HW mode.
36 // A class used to associate objects with HW modes. It is only intended to
46 // dependent on a HW mode. This class inherits from ValueType itself,
64 // The register size/alignment information, parameterized by a HW mode.
220 // The register size/alignment information, parameterized by a HW mode.
/llvm-project-15.0.7/mlir/test/Integration/Dialect/Vector/CPU/X86Vector/
H A Dtest-sparse-dot-product.mlir8 // the dot product of two sparse HW vectors of 8 float64 elements ("segment").
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARM.td36 // Floating Point, HW Division and Neon Support
441 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
/llvm-project-15.0.7/openmp/runtime/src/include/
H A Domp-tools.h.var109 macro (kmp_mutex_impl_speculative, 3) /* based on HW-supported speculation */

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