Lines Matching refs:HW

48     almost 1-1 with the HW ISA. This is referred to as the Hardware Vector
86 hardware, we are auto-generating the specific HW dialects. For `GPU`, the `NVVM`
171 `vector` types that are multiples of a "good" `vector` size so the HW can
173 `vector<8x8x8x16xf32>` when HW `vector` size is say `vector<4x8xf32>`).
182 3.  Other accelerators: n-D `vector` as first-class citizens in the HW.
184 Depending on the target, ops on sizes that are not multiples of the HW `vector`
192 “unrolled” to HW-specific sizes. The multi-dimensional unrolling factors are
322 model, execution on actual HW and what is visible or hidden from codegen. They
359 2.  Hides away the real HW structure behind dynamic indexing: at the end of the
360     day, HW vector sizes are generally fixed and multiple vectors will be needed
361     to hold a vector that is larger than the HW.
363     accesses, especially at HW vector boundaries unlikely to result in regular
368 #### HW Vectors and Implications on the SW and the Programming Model
371 unsurprising because historically, the vast majority of HW only supports `1-D`
372 vector registers. We note that multiple HW vendors are in the process of
375 In the following discussion, let's assume the HW vector size is `1-D` and the SW
377 HW `vector` size and `n >= 2`. In this context, most HW exhibit a vector
379 sizes of the SW vector abstraction and the HW vector sizes and number of
381 `1-D` HW vector registers + memory locations at a given point in time.
383 The implication of the physical HW constraints on the programming model are that
408     correspond to the HW. This level of MLIR codegen is related to register
410 3.  HW may support >1-D vectors with intrinsics for indirect addressing within
419 Different HW will require different tradeoffs in the sizes involved in steps 1.,
480 HW-specific world with special intrinsics. This is a good abstraction for
484 target operations on coarser-grained vectors than the HW size and on which
485 unroll-and-jam is applied and patterns across multiple HW vectors can be