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Searched refs:Greedy (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/mlir/include/mlir/Dialect/Affine/
H A DPasses.h29 enum FusionMode { Greedy, ProducerConsumer, Sibling }; enumerator
77 enum FusionMode fusionMode = FusionMode::Greedy);
H A DPasses.td167 "mlir::FusionMode::Greedy", "fusion mode to attempt",
168 "llvm::cl::values(clEnumValN(mlir::FusionMode::Greedy,"
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-regalloc-flags.ll18 ; DEFAULT: Greedy Register Allocator
23 ; DEFAULT-NEXT: Greedy Register Allocator
51 ; BASIC-DEFAULT-NEXT: Greedy Register Allocator
58 ; DEFAULT-BASIC: Greedy Register Allocator
H A Dllc-pipeline.ll340 ; GCN-O1-NEXT: Greedy Register Allocator
345 ; GCN-O1-NEXT: Greedy Register Allocator
630 ; GCN-O1-OPTS-NEXT: Greedy Register Allocator
635 ; GCN-O1-OPTS-NEXT: Greedy Register Allocator
922 ; GCN-O2-NEXT: Greedy Register Allocator
927 ; GCN-O2-NEXT: Greedy Register Allocator
1227 ; GCN-O3-NEXT: Greedy Register Allocator
1232 ; GCN-O3-NEXT: Greedy Register Allocator
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DRegBankSelect.rst60 * **Greedy** --- For each instruction, pick the cheapest of several
69 On AArch64, we are considering using the Greedy mode even at -O0 (or perhaps at
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DCGPassBuilderOption.h24 enum class RegAllocType { Default, Basic, Fast, Greedy, PBQP }; enumerator
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-opt-remarks-lazy-bfi.ll26 ; HOTNESS-NEXT: Executing Pass 'Greedy Register Allocator'
H A DO3-pipeline.ll173 ; CHECK-NEXT: Greedy Register Allocator
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dopt-pipeline.ll147 ; CHECK-NEXT: Greedy Register Allocator
149 ; CHECK-NEXT: Greedy Register Allocator
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegBankSelect.h102 Greedy enumerator
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A DO3-pipeline.ll122 ; CHECK-NEXT: Greedy Register Allocator
/llvm-project-15.0.7/llvm/docs/CommandGuide/
H A Dllc.rst185 Greedy register allocator. It is the default for optimized code.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A DO3-pipeline.ll133 ; CHECK-NEXT: Greedy Register Allocator
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DDecoderEmitter.cpp551 bool filterProcessor(bool AllowMixed, bool Greedy = true);
1532 bool FilterChooser::filterProcessor(bool AllowMixed, bool Greedy) { in filterProcessor() argument
1545 if (AllowMixed && !Greedy) { in filterProcessor()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A DO3-pipeline.ll166 ; CHECK-NEXT: Greedy Register Allocator
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-regbankselect.mir315 ; Greedy mode remapped the instruction on the GPR bank.
348 ; Greedy mode remapped the instruction on the GPR bank.
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp57 clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy",
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DCodeGenPassBuilder.h1020 else if (Opt.RegAlloc == RegAllocType::Greedy) in addRegAllocPass()
/llvm-project-15.0.7/llvm/
H A DCREDITS.TXT385 D: Greedy register allocator
/llvm-project-15.0.7/mlir/docs/
H A DPatternRewriter.md323 ### Greedy Pattern Rewrite Driver
H A DBufferization.md53 * **Greedy**: Operations are analyzed one-by-one and it is decided on the spot
/llvm-project-15.0.7/llvm/docs/
H A DCodeGenerator.rst1493 * *Greedy* --- *The default allocator*. This is a highly tuned implementation of