| /llvm-project-15.0.7/compiler-rt/lib/xray/tests/unit/ |
| H A D | buffer_queue_test.cpp | 63 Buf.Generation = Buffers.generation(); in TEST()
139 ASSERT_NE(B0.Generation, B1.Generation); in TEST()
142 auto PrevGen = B1.Generation; in TEST()
160 EXPECT_NE(B0.Generation, PrevGen); in TEST()
161 EXPECT_EQ(B1.Generation, B1.Generation); in TEST()
182 auto FirstGen = B.Generation; in TEST()
203 EXPECT_NE(FirstGen, B.Generation); in TEST()
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| /llvm-project-15.0.7/compiler-rt/lib/xray/ |
| H A D | xray_buffer_queue.cpp | 111 atomic_fetch_add(&Generation, 1, memory_order_acq_rel); in init()
128 Buf.Generation = generation(); in init()
157 Generation{0} {
179 Buf.Generation = generation(); in getBuffer()
190 if (Buf.Generation != generation() || LiveBuffers == 0) { in releaseBuffer()
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| H A D | xray_fdr_controller.h | 47 return B.Data != nullptr && B.Generation == BQ->generation() && in hasSpace()
154 if (B.Generation != BQ->generation()) in recordPreamble()
171 if (B.Generation != BQ->generation()) in recordPreamble()
191 if (B.Generation != BQ->generation()) in rewindRecords()
210 if (B.Generation != BQ->generation()) in rewindRecords()
217 if (B.Generation != BQ->generation()) in rewindRecords()
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| H A D | xray_buffer_queue.h | 56 uint64_t Generation{0};
164 atomic_uint64_t Generation; variable
237 return atomic_load(&Generation, memory_order_acquire); in generation()
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| H A D | xray_fdr_logging.cpp | 466 if (TLD.Buffer.Generation != BQ->generation() && in setupTLD()
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| /llvm-project-15.0.7/clang/include/clang/Serialization/ |
| H A D | ModuleFile.h | 113 ModuleFile(ModuleKind Kind, unsigned Generation) in ModuleFile() argument
114 : Kind(Kind), Generation(Generation) {} in ModuleFile()
185 unsigned Generation; variable
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| H A D | ModuleManager.h | 245 ModuleFile *ImportedBy, unsigned Generation,
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | Module.h | 739 : ImportLocs(std::move(O.ImportLocs)), Generation(O.Generation ? 1 : 0) { in VisibleModuleSet()
741 ++O.Generation; in VisibleModuleSet()
749 ++O.Generation;
750 ++Generation;
756 unsigned getGeneration() const { return Generation; } in getGeneration()
793 unsigned Generation = 0; variable
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600Subtarget.h | 41 Generation Gen = R600;
75 Generation getGeneration() const { in getGeneration()
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| H A D | AMDGPUSubtarget.h | 31 enum Generation { enum
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| H A D | GCNSubtarget.h | 264 Generation getGeneration() const { in getGeneration()
265 return (Generation)Gen; in getGeneration()
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| H A D | SIMemoryLegalizer.cpp | 842 GCNSubtarget::Generation Generation = ST.getGeneration(); in create() local
847 if (Generation <= AMDGPUSubtarget::SOUTHERN_ISLANDS) in create()
849 if (Generation < AMDGPUSubtarget::GFX10) in create()
851 if (Generation < AMDGPUSubtarget::GFX11) in create()
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| /llvm-project-15.0.7/clang/lib/Basic/Targets/ |
| H A D | Sparc.cpp | 64 SparcTargetInfo::CPUGeneration Generation; member
120 return Item->Generation; in getCPUGeneration()
258 if (Info.Generation == CG_V9) in fillValidCPUList()
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | DiscourseMigrationGuide.md | 53 <tr><td>Code Generation</td><td>[email protected]</td></tr>
54 <tr><td>Code Generation - AMDGPU</td><td>[email protected]</td></tr>
55 <tr><td>Code Generation - Common Infrastructure</td><td>[email protected]</td></tr>
56 <tr><td>Code Generation - AArch64</td><td>[email protected]</td></tr>
57 <tr><td>Code Generation - Arm</td><td>[email protected]</td></tr>
58 <tr><td>Code Generation - PowerPC</td><td>[email protected]</td></tr>
59 <tr><td>Code Generation - RISCV</td><td>[email protected]</td></tr>
60 <tr><td>Code Generation - WebAssembly</td><td>[email protected]</td></tr>
61 <tr><td>Code Generation - X86</td><td>[email protected]</td></tr>
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| H A D | UserGuides.rst | 175 Code Generation
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 554 unsigned Generation = 0; member
559 LoadValue(Instruction *Inst, unsigned Generation, unsigned MatchingId, in LoadValue()
561 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), in LoadValue()
1157 if (!isOperatingOnInvariantMemAt(MemInst.get(), InVal.Generation) && in getMatchingValue()
1158 !isSameMemGeneration(InVal.Generation, CurrentGeneration, InVal.DefInst, in getMatchingValue()
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| /llvm-project-15.0.7/clang/lib/Serialization/ |
| H A D | ModuleManager.cpp | 105 unsigned Generation, in addModule() argument
170 auto NewModule = std::make_unique<ModuleFile>(Type, Generation); in addModule()
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| /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/ |
| H A D | store-abs.ll | 6 ; Generation of absolute pattern for a 64 bit truncated value also aviods an
|
| /llvm-project-15.0.7/polly/lib/External/isl/imath/tests/gmp-compat-test/ |
| H A D | README | 50 Testcase Generation
|
| /llvm-project-15.0.7/mlir/include/mlir/Dialect/SparseTensor/IR/ |
| H A D | SparseTensorBase.td | 70 Proceedings of the IEEE/ACM International Symposium on Code Generation
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MSA.txt | 1 Code Generation Notes for MSA
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCV.td | 132 "'Zba' (Address Generation Instructions)">;
135 "'Zba' (Address Generation Instructions)">;
|
| /llvm-project-15.0.7/llvm/docs/tutorial/MyFirstLanguageFrontend/ |
| H A D | LangImpl03.rst | 25 Code Generation Setup
115 Expression Code Generation
258 Function Code Generation
|
| /llvm-project-15.0.7/clang/docs/ |
| H A D | MSVCCompatibility.rst | 81 * RTTI: :good:`Complete`. Generation of RTTI data structures has been
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | O3-pipeline.ll | 202 ; CHECK-NEXT: PowerPC Expand ISEL Generation
|