Home
last modified time | relevance | path

Searched refs:GPR64RegClass (Results 1 – 25 of 26) sorted by relevance

12

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
67 const MCRegisterClass *GPR64RegClass; variable
H A DMipsMachineFunction.cpp49 return Mips::GPR64RegClass; in getGlobalBaseRegClass()
81 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
161 ? Mips::GPR64RegClass in createEhDataRegsFI()
H A DMipsSERegisterInfo.cpp59 return &Mips::GPR64RegClass; in intRegClass()
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
H A DMipsSEInstrInfo.cpp149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg()
150 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg()
256 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
334 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
628 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
H A DMipsSEFrameLowering.cpp422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
719 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
893 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
909 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
H A DMipsSubtarget.cpp234 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass in getCriticalPathRCs()
H A DMipsRegisterInfo.cpp54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
H A DMipsSEISelLowering.cpp71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
3330 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3516 : &Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3522 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3568 : &Mips::GPR64RegClass); in emitLD_F16_PSEUDO()
3660 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPROUND_PSEUDO()
3764 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPEXTEND_PSEUDO()
H A DMipsISelLowering.cpp4141 return std::make_pair(0U, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
4165 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
4828 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitLDR_D()
4963 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitSTR_D()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp108 const MCRegisterClass *GPR64RegClass = in hasLiveDefs() local
119 RegIsGPR64 = GPR64RegClass->contains(MO.getReg()); in hasLiveDefs()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp411 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
472 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
1715 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs()
1817 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1831 RC = &AArch64::GPR64RegClass; in emitLoad()
2670 RC = &AArch64::GPR64RegClass; in selectSelect()
2962 RC = &AArch64::GPR64RegClass; in fastLowerArguments()
3231 CallReg = createResultReg(&AArch64::GPR64RegClass); in fastLowerCall()
4752 case MVT::i64: RC = &AArch64::GPR64RegClass; break; in selectBitCast()
4845 RC = &AArch64::GPR64RegClass; in selectSDiv()
[all …]
H A DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
110 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
H A DAArch64CleanupLocalDynamicTLSPass.cpp126 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
H A DAArch64RegisterInfo.cpp380 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. in getCrossCopyRegClass()
675 MI.getMF()->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in createScratchRegisterForInstruction()
767 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
H A DAArch64FrameLowering.cpp849 for (unsigned Reg : AArch64::GPR64RegClass) { in findScratchNonCalleeSaveRegister()
2550 if (AArch64::GPR64RegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs()
2569 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
2982 if (AArch64::GPR64RegClass.contains(Reg) || in determineCalleeSaves()
2988 if (AArch64::GPR64RegClass.contains(Reg) && in determineCalleeSaves()
3002 if (AArch64::GPR64RegClass.contains(PairedReg) && in determineCalleeSaves()
3087 const TargetRegisterClass &RC = AArch64::GPR64RegClass; in determineCalleeSaves()
3414 Register ScratchReg = MRI->createVirtualRegister(&AArch64::GPR64RegClass); in emitUnrolled()
3451 : MRI->createVirtualRegister(&AArch64::GPR64RegClass); in emitLoop()
3452 Register SizeReg = MRI->createVirtualRegister(&AArch64::GPR64RegClass); in emitLoop()
H A DAArch64InstrInfo.cpp738 RC = &AArch64::GPR64RegClass; in insertSelect()
4287 &AArch64::GPR64RegClass); in emitFrameOffsetAdj()
4522 SpillRC = &AArch64::GPR64RegClass; in foldMemoryOperandImpl()
5772 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
5787 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
5813 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
5855 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
5879 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
5905 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
6944 for (unsigned Reg : AArch64::GPR64RegClass) { in findRegisterToSaveLRTo()
[all …]
H A DAArch64CollectLOH.cpp506 for (MCPhysReg Reg : AArch64::GPR64RegClass) in handleNormalInst()
H A DAArch64FalkorHWPFFix.cpp751 for (unsigned ScratchReg : AArch64::GPR64RegClass) { in runOnLoop()
H A DAArch64LoadStoreOptimizer.cpp1129 LdRt, AArch64::sub_32, &AArch64::GPR64RegClass)) in promoteLoadFromStore()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/AArch64/
H A DTarget.cpp48 if (AArch64::GPR64RegClass.contains(Reg)) in setRegTo()
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp152 if (Mips::GPR64RegClass.contains(Reg)) in setRegTo()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp522 : &AArch64::GPR64RegClass; in getRegClassForTypeOnBank()
560 : &AArch64::GPR64RegClass; in getMinClassForRegBank()
2001 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass); in preISelLower()
3100 SrcRC == &AArch64::GPR64RegClass) { in select()
3284 {&AArch64::GPR64RegClass}, {}) in select()
3562 IsSet ? AArch64::GPR64RegClass : AArch64::GPR64commonRegClass; in selectMOPS()
3567 RBI.constrainGenericRegister(SizeCopy, AArch64::GPR64RegClass, MRI); in selectMOPS()
4011 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues()
5293 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in selectUSMovFromExtend()
5814 RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI); in selectIntrinsic()
[all …]
H A DAArch64LegalizerInfo.cpp957 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
979 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
1372 auto Scratch = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in legalizeAtomicCmpxchg128()
H A DAArch64CallLowering.cpp514 Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in handleMustTailForwardedRegisters()

12