378   const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass  in materializeInt()
411         &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in materializeFP()
472       ResultReg = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
485     Register Result64 = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
1301       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rr()
1344     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_ri()
1387       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rs()
1429     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rx()
1715     RC = &AArch64::GPR64RegClass;  in emitLogicalOp_rs()
1817              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1822              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1827              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1831     RC = &AArch64::GPR64RegClass;  in emitLoad()
1859     Register Reg64 = createResultReg(&AArch64::GPR64RegClass);  in emitLoad()
2670     RC = &AArch64::GPR64RegClass;  in selectSelect()
2829       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2962       RC = &AArch64::GPR64RegClass;  in fastLowerArguments()
3231       CallReg = createResultReg(&AArch64::GPR64RegClass);  in fastLowerCall()
3423     Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in fastLowerIntrinsicCall()
3434       DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,  in fastLowerIntrinsicCall()
3946       Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in emiti1Ext()
3979       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitMul_rr()
3987   return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,  in emitSMULL_rr()
3995   return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,  in emitUMULL_rr()
4013       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSL_rr()
4038       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSL_ri()
4115       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSR_rr()
4141       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSR_ri()
4231       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitASR_rr()
4257       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitASR_ri()
4369     Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in emitIntExt()
4379       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4466     Register Reg64 = createResultReg(&AArch64::GPR64RegClass);  in optimizeIntExtLoad()
4509         Register ResultReg = createResultReg(&AArch64::GPR64RegClass);  in selectIntExt()
4562       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()
4752   case MVT::i64: RC = &AArch64::GPR64RegClass; break;  in selectBitCast()
4845     RC = &AArch64::GPR64RegClass;  in selectSDiv()
4986     ResRC = &AArch64::GPR64RegClass;  in selectAtomicCmpXchg()