| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.h | 112 bool ForCodeSize) const override;
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| H A D | LoongArchISelLowering.cpp | 1091 bool ForCodeSize) const { in isFPImmLegal()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.h | 170 bool LegalOperations, bool ForCodeSize,
183 bool ForCodeSize) const override;
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| H A D | AMDGPUISelLowering.cpp | 620 bool ForCodeSize) const { in isFPImmLegal()
730 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, in getNegatedExpression() argument
746 ForCodeSize, Cost, Depth); in getNegatedExpression()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.h | 213 bool ForCodeSize) const override;
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| H A D | VEISelLowering.cpp | 863 bool ForCodeSize) const { in isFPImmLegal()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1016 bool LegalOperations, bool ForCodeSize,
1316 bool ForCodeSize) const override;
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| H A D | X86ISelLowering.cpp | 5680 bool ForCodeSize) const { in isFPImmLegal()
50784 bool ForCodeSize, in getNegatedExpression() argument
50821 Op.getOperand(i), DAG, LegalOperations, ForCodeSize, Depth + 1); in getNegatedExpression()
50840 ForCodeSize, Cost, Depth + 1)) in getNegatedExpression()
50846 ForCodeSize, Cost, Depth); in getNegatedExpression()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 382 bool ForCodeSize) const override;
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| H A D | RISCVISelLowering.cpp | 1345 bool ForCodeSize) const { in isFPImmLegal()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 444 bool ForCodeSize) const override;
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| H A D | SystemZISelLowering.cpp | 836 bool ForCodeSize) const { in isFPImmLegal()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 673 bool ForCodeSize) const override;
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| H A D | MipsISelLowering.cpp | 4325 bool ForCodeSize) const { in isFPImmLegal()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 149 bool ForCodeSize; member in __anon54f00e400111::DAGCombiner
240 ForCodeSize = DAG.shouldOptForSize(); in DAGCombiner()
14632 N1, DAG, LegalOperations, ForCodeSize)) in visitFADD()
14638 N0, DAG, LegalOperations, ForCodeSize)) in visitFADD()
15542 if (ForCodeSize) in visitFPOW()
16917 bool ForCodeSize = false; member
16926 explicit Cost(bool ForCodeSize) : ForCodeSize(ForCodeSize) {} in Cost()
16929 Cost(const LoadedSlice &LS, bool ForCodeSize) in Cost()
16930 : ForCodeSize(ForCodeSize), Loads(1) { in Cost()
17325 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize); in isSlicingProfitable()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 294 bool ForCodeSize) const override;
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| H A D | HexagonISelLowering.cpp | 3427 bool ForCodeSize) const { in isFPImmLegal()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 603 bool ForCodeSize = false) const override;
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| H A D | ARMISelLowering.cpp | 20672 bool ForCodeSize) const { in isFPImmLegal()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 1133 bool ForCodeSize) const override;
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| H A D | PPCISelLowering.cpp | 16945 bool ForCodeSize) const { in isFPImmLegal()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 546 bool ForCodeSize) const override;
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| H A D | AArch64InstrInfo.td | 763 def ForCodeSize : Predicate<"shouldOptForSize(MF)">;
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1060 bool ForCodeSize = false) const {
|